UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 109

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address
F0144H
F0145H
F0146H
F0147H
F0148H
F0149H
F014AH
F014BH
F014EH
F014FH
F0150H
F0151H
F0152H
F0153H
F0154H
F0155H
F0156H
F0157H
F0158H
F0159H
F015AH
F015BH
F015CH
F015DH
F015EH
F015FH
F0160H
F0161H
F0162H
F0163H
F0164H
F0165H
F0166H
F0167H
F0168H
F0169H
F016AH
F016BH
Serial status register 12
Serial status register 13
Serial flag clear trigger register 10
Serial flag clear trigger register 11
Serial flag clear trigger register 13
Serial mode register 10
Serial mode register 11
Serial mode register 12
Serial mode register 13
Serial communication operation setting
register 10
Serial communication operation setting
register 11
Serial communication operation setting
register 12
Serial communication operation setting
register 13
Serial channel enable status register 1
Serial channel start register 1
Serial channel stop register 1
Serial clock select register 1
Serial output register 1
Serial output enable register 1
Special Function Register (SFR) Name
Table 3-6. Extended SFR (2nd SFR) List (3/8)
SSR12L
SSR13L
SIR10L
SIR11L
SIR13L
SMR10
SMR11
SMR12
SMR13
SCR10
SCR11
SCR12
SCR13
SE1L
SS1L
ST1L
SPS1L
SO1
SOE1L
−
−
−
−
−
−
−
−
−
−
Symbol
SSR12
SSR13
SIR10
SIR11
SIR13
SE1
SS1
ST1
SPS1
SOE1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
Manipulable Bit Range
1-bit
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
−
√
−
√
−
−
−
−
√
−
CHAPTER 3 CPU ARCHITECTURE
8-bit
√
−
√
−
√
−
√
−
√
−
−
−
−
−
−
−
−
−
√
−
√
−
√
−
√
−
−
√
−
16-bit
√
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√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
0F0FH
0000H
0000H
0000H
0000H
0000H
0020H
0020H
0020H
0020H
0087H
0087H
0087H
0087H
0000H
0000H
0000H
0000H
0000H
Reset
After
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