UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 674

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Symbol
LCDC0
Address: FFF42H
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(3)
Caution
Other than above
LCD clock control register (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC0 is set using an 8-bit memory manipulation instruction.
Reset signal generation sets LCDC0 to 00H.
LCDC5
LCDC2
7
0
0
0
1
1
0
0
0
0
1
1
5. To manipulate VLCON when using the internal voltage boosting method or capacitor split
After reset:
method, follow the procedure below.
A. To stop the operation of the voltage boosting/capacitor split circuit after switching display
B. To stop the operation of the voltage boosting/capacitor split circuit during display on status:
C. To set display on from stop status of the voltage boosting/capacitor split circuit:
status from on to off:
1) Set to display off status by setting LCDON = 0.
2) Disable outputs of all the segment buffers and common buffers by setting SCOC = 0.
3) Stop the operation of the voltage boosting/capacitor split circuit by setting VLCON = 0.
Setting prohibited. Be sure to stop the operation of the voltage boosting/capacitor split
circuit after setting display off.
1) Start the operation of the voltage boosting/capacitor split circuit by setting VLCON = 1,
2) Set all the segment buffers and common buffers to non-display output status by setting
3) Set display on by setting LCDON = 1.
LCDC4
LCDC1
then wait for the voltage boosting/capacitor split wait time (see CHAPTER 31
ELECTRICAL SPECIFICATIONS).
SCOC = 1.
6
0
0
1
0
1
0
0
1
1
0
0
Figure 16-4. Format of LCD Clock Control Register (LCDC0)
00H
f
f
f
f
R/W
SUB
CLK
CLK
CLK
LCDC5
LCDC0
/2
/2
/2
6
7
8
5
0
1
0
1
0
1
f
f
f
f
f
f
Setting prohibited
LCD
LCD
LCD
LCD
LCD
LCD
LCDC4
/2
/2
/2
/2
/2
/2
4
5
6
7
8
9
4
LCD source clock (f
3
0
LCD clock (LCDCL) selection
CHAPTER 16 LCD CONTROLLER/DRIVER
LCD
LCDC2
) selection
2
LCDC1
1
LCDC0
0
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