UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 271

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F0190H, F0191H (TMR00) to F019EH, F019FH (TMR07)
(3) Timer mode register mn (TMRmn)
TMRmn
Symbol
TMRmn sets an operation mode of channel n of timer array unit m. It is used to select an operation clock (MCK), a
count clock, whether the timer operates as the master or a slave, a start trigger and a capture trigger, the valid
edge of the timer input, and an operation mode (interval, capture, event counter, one-count, or capture & one-
count).
Rewriting TMRmn is prohibited when the register is in operation (when TEm = 1). However, bits 7 and 6 (CISmn1,
CISmn0) can be rewritten even while the register is operating with some functions (when TEm = 1) (for details, see
6.7 Operation of Timer Array Unit as Independent Channel and 6.8 Operation of Plural Channels of Timer
Array Unit).
TMRmn can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Remark
Caution Be sure to clear bits 14, 13, 5, and 4 to “0”.
F01C8H, F01C9H (TMR10) to F01CEH, F01CFH (TMR13)
Operation clock MCK is used by the edge detector. A count clock (TCLK) and a sampling clock are generated
depending on the setting of the CCSmn bit.
Count clock TCLK is used for the timer/counter, output controller, and interrupt controller.
If CCSmn = 1, use the count clock under the following condition.
CKS
CCS
CKS
• The frequency of the operating clock selected by using CKSmn ≥ The frequency of the clock selected by using
mn
mn
mn
15
0
1
0
1
TISmn × 2
mn: Unit number + Channel number, pq: Unit number + Channel number (only for channels provided with
timer I/O pins)
78K0R/LF3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 04, 07
78K0R/LG3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07
78K0R/LH3: m = 0, 1, mn = 00 to 07, 10 to 13, pq = 00 to 07, 10 to 13
Operation clock CKm0 set by TPSm register
Operation clock CKm1 set by TPSm register
Operation clock MCK specified by CKSmn bit
Valid edge of input signal input from TIpq pin, f
is selected by using TISm register).
14
0
Figure 6-7. Format of Timer Mode Register mn (TMRmn) (1/4)
13
0
CCS
mn
12
MAST
ERmn
11
STS
mn2
Selection of operation clock (MCK) of channel n
10
Selection of count clock (TCLK) of channel n
STS
mn1
9
STS
mn0
8
SUB
After reset: 0000H
/2, f
mn1
CIS
SUB/
7
4, or INTRTC1 (the timer input used with channel x
mn0
CIS
6
CHAPTER 6 TIMER ARRAY UNIT
5
0
R/W
4
0
mn3
MD
3
mn2
MD
2
mn1
MD
1
mn0
MD
0
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