UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 542

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UPD78F1506GF-GAT-AX

Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet

Specifications of UPD78F1506GF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(Essential)
(Selective)
(Selective)
(Selective)
(Selective)
(Essential)
(Selective)
(Essential)
(Essential)
Changing setting of SOEm register
Changing setting of SPSm register
Changing setting of SDRmn register
Changing setting of SCRmn register
Manipulating target for communication
Changing setting of SMRmn
Starting setting for resumption
Starting communication
Figure 14-79. Procedure for Resuming UART Reception
Writing to SSm
and SMRmr registers
Clearing error flag
register
Stop the target for communication or wait
until the target completes its operation.
Change the setting if an incorrect division
ratio of the operation clock is set.
Change the setting if an incorrect
transfer baud rate is set.
Change the setting if the setting of the
SMRmn and SMRmr registers is incorrect.
Change the setting if the setting of the
SCRmn register is incorrect.
Clear the SOEm register to 0 and stop
data output of the target channel.
Cleared by using SIRm register if FEF,
PEF, or OVF flag remains set.
Set the SSmn bit of the target channel to
1 to set SEmn = 1.
The start bit is detected.
CHAPTER 14 SERIAL ARRAY UNIT
542

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