UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 801

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
Notes 1.
Remark
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Reset function
Low-voltage detector
DMA controller
Interrupt
Regulator
BCD correction circuit
(BCD)
2.
3.
Register
RESF
LVIS
During reset signal generation or oscillation stabilization time wait, only the PC contents among the hardware
statuses become undefined. All other hardware statuses remain unchanged after reset.
These values vary depending on the reset source.
This value varies depending on the reset source and the option byte.
The SFR and 2nd SFR mounted depend on the product. Refer to 3.2.4 Special function registers (SFRs)
and 3.2.5 Extended special function registers (2nd SFRs: 2nd Special Function Registers).
Reset Source
TRAP bit
WDRF bit
LVIRF bit
Table 22-2. Hardware Statuses After Reset Acknowledgment (4/4)
Reset control flag register (RESF)
Low-voltage detection register (LVIM)
Low-voltage detection level select register (LVIS)
SFR address registers 0, 1 (DSA0, DSA1)
RAM address registers 0L, 0H, 1L, 1H (DRA0L, DRA0H, DRA1L, DRA1H)
Byte count registers 0L, 0H, 1L, 1H (DBC0L, DBC0H, DBC1L, DBC1H)
Mode control registers 0, 1 (DMC0, DMC1)
Operation control registers 0, 1 (DRC0, DRC1)
Request flag registers 0L, 0H, 1L, 1H, 2L, 2H (IF0L, IF0H, IF1L, IF1H,
IF2L, IF2H)
Mask flag registers 0L, 0H, 1L, 1H, 2L, 2H (MK0L, MK0H, MK1L,
MK1H, MK2L, MK2H)
Priority specification flag registers 00L, 00H, 01L, 01H, 02L, 02H, 10L,
10H, 11L, 11H, 12L, 12H (PR00L, PR00H, PR01L, PR01H, PR10L,
PR10H, PR11L, PR11H, PR02L, PR02H, PR12L, PR12H)
External interrupt rising edge enable registers 0, 1 (EGP0, EGP1)
External interrupt falling edge enable registers 0, 1 (EGN0, EGN1)
Regulator mode control register (RMC)
BCD correction result register (BCDADJ)
Cleared (0)
Cleared (0EH)
RESET Input
Hardware
Cleared (0)
Cleared (0EH)
Reset by POC
Set (1)
Held
Held
Cleared (0EH)
Reset by Execution of
Illegal Instruction
CHAPTER 22 RESET FUNCTION
Held
Set (1)
Held
Cleared (0EH)
Reset by WDT
Undefined
00H
0EH
00H
00H
00H
00H
00H
00H
FFH
FFH
00H
00H
00H
Undefined
Acknowledgment
Status After Reset
Note 3
Note 2
Held
Held
Set (1)
Held
Reset by LVI
Note 2
Note 1
801