FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 10

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

10
5.16
5.17
5.15.2 Bus Master Function ....................................................................... 178
5.15.3 Ultra ATA/33 Protocol ..................................................................... 182
5.15.4 Ultra ATA/66 Protocol ..................................................................... 184
5.15.5 Ultra ATA/100 Protocol ................................................................... 184
5.15.6 Ultra ATA/33/66/100 Timing ........................................................... 185
5.15.7 IDE Swap Bay................................................................................. 185
USB UHCI Controllers (D29:F0, F1 and F2)................................................ 186
5.16.1 Data Structures in Main Memory .................................................... 186
5.16.2 Data Transfers to/from Main Memory ............................................. 192
5.16.3 Data Encoding and Bit Stuffing ....................................................... 198
5.16.4 Bus Protocol ................................................................................... 198
5.16.5 Packet Formats............................................................................... 201
5.16.6 USB Interrupts ................................................................................ 203
5.16.7 USB Power Management ............................................................... 206
5.16.8 USB Legacy Keyboard Operation................................................... 206
USB EHCI Controller (D29:F7) .................................................................... 209
5.17.1 EHC Initialization ............................................................................ 209
5.15.1.6 PIO IDE Data Port Prefetching and Posting.................... 178
5.15.2.1 Physical Region Descriptor Format................................. 178
5.15.2.2 Line Buffer ....................................................................... 179
5.15.2.3 Bus Master IDE Timings.................................................. 179
5.15.2.4 Interrupts ......................................................................... 179
5.15.2.5 Bus Master IDE Operation .............................................. 180
5.15.2.6 Error Conditions .............................................................. 182
5.15.2.7 8237-Like Protocol .......................................................... 182
5.15.3.1 Signal Descriptions.......................................................... 183
5.15.3.2 Operation......................................................................... 183
5.15.3.3 CRC Calculation.............................................................. 184
5.16.1.1 Frame List Pointer ........................................................... 186
5.16.1.2 Transfer Descriptor (TD) ................................................. 187
5.16.1.3 Queue Head (QH) ........................................................... 191
5.16.2.1 Executing the Schedule................................................... 192
5.16.2.2 Processing Transfer Descriptors ..................................... 193
5.16.2.3 Command Register, Status Register, and TD Status Bit
5.16.2.4 Transfer Queuing ............................................................ 195
5.16.4.1 Bit Ordering ..................................................................... 198
5.16.4.2 SYNC Field...................................................................... 198
5.16.4.3 Packet Field Formats ...................................................... 198
5.16.4.4 Address Fields................................................................. 200
5.16.4.5 Frame Number Field ....................................................... 200
5.16.4.6 Data Field ........................................................................ 200
5.16.4.7 Cyclic Redundancy Check (CRC) ................................... 201
5.16.5.1 Token Packets................................................................. 201
5.16.5.2 Start of Frame Packets.................................................... 201
5.16.5.3 Data Packets ................................................................... 202
5.16.5.4 Handshake Packets ........................................................ 202
5.16.5.5 Handshake Responses ................................................... 203
5.16.6.1 Transaction Based Interrupts .......................................... 203
5.16.6.2 Non-Transaction Based Interrupts .................................. 205
5.17.1.1 Power On ........................................................................ 209
5.17.1.2 BIOS Initialization ............................................................ 209
5.17.1.3 Driver Initialization ........................................................... 210
5.17.1.4 EHC Resets..................................................................... 210
Interaction........................................................................ 194
Intel
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82801DBM ICH4-M Datasheet