FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 603

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Table A-3. Intel
Intel
Command Register Primary
Status Register Primary
Descriptor Table Pointer Primary
Command Register Secondary
Status Register Secondary
Descriptor Table Pointer
Secondary
USB Command Register
USB Status Register
USB Interrupt Enable
USB Frame Number
USB Frame List Base Address
USB Start of Frame Modify
Port 0, 2, 4 Status/Control
Port 1, 3, 5 Status/Control
Host Status
Host Control
Host Command
Transmit Slave Address
Host Data 0
Host Data 1
Block Data Byte
Packet Error Check
Receive Slave Address
Receive Slave Data
USB Base Address is set at Section 11.1.10, “BASE—Base Address Register (USB—D29:F0/F1/F2)” on page 11-423
BM_BASE is set at Section 10.1.12, “SCMD_BAR—Secondary Command Block Base Address Register (IDE D31:F1)” on
SMB_BASE is set at Section 13.1.8, “SMB_BASE—SMBUS Base Address Register (SMBUS—D31:F3)” on page 13-476
®
82801DBM ICH4-M Datasheet
Register Name
®
ICH4 Variable I/O Registers (Sheet 3 of 6)
0C–0Fh
08–0Bh
04–07h
00–01h
02–03h
04–05h
06–07h
10–11h
12–13h
Offset
0Ch
SMBus I/O Registers at SMB_BASE + Offset
0Ah
USB I/O Registers at Base Address + Offset
0Ah
00h
02h
08h
00h
02h
03h
04h
05h
06h
07h
08h
09h
BMIDE I/O Registers at BM_BASE + Offset
Section 10.2.1, “BMIC[P,S]—Bus Master IDE Command Register” on
page 10-415
Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status Register” on
page 10-416
Section 10.2.3, “BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register” on page 10-417
Section 10.2.1, “BMIC[P,S]—Bus Master IDE Command Register” on
page 10-415
Section 10.2.2, “BMIS[P,S]—Bus Master IDE Status Register” on
page 10-416
Section 10.2.3, “BMID[P,S]—Bus Master IDE Descriptor Table Pointer
Register” on page 10-417
Section 11.2.1, “USBCMD—USB Command Register” on page 11-428
Section 11.2.2, “USBSTS—USB Status Register” on page 11-431
Section 11.2.3, “USBINTR—Interrupt Enable Register” on page 11-432
Section 11.2.4, “FRNUM—Frame Number Register” on page 11-432
Section 11.2.5, “FRBASEADD—Frame List Base Address” on page 11-433
Section 11.2.6, “SOFMOD—Start of Frame Modify Register” on page 11-434
Section 11.2.7, “PORTSC[0,1]—Port Status and Control Register” on
page 11-435
Section 11.2.7, “PORTSC[0,1]—Port Status and Control Register” on
page 11-435
Section 13.2.1, “HST_STS—Host Status Register” on page 13-478
Section 13.2.2, “HST_CNT—Host Control Register” on page 13-480
Section 13.2.3, “HST_CMD—Host Command Register” on page 13-481
Section 13.2.4, “XMIT_SLVA—Transmit Slave Address Register” on
page 13-481
Section 13.2.5, “HST_D0—Data 0 Register” on page 13-481
Section 13.2.6, “HST_D1—Data 1 Register” on page 13-482
Section 13.2.7, “Host_BLOCK_DB—Host Block Data Byte Register” on
page 13-482
Section 13.2.8, “PEC—Packet Error Check (PEC) Register” on page 13-482
Section 13.2.9, “RCV_SLVA—Receive Slave Address Register” on
page 13-483
Section 13.2.10, “SLV_DATA—Receive Slave Data Register” on
page 13-483
page 10-406
Datasheet Location
Register Index
603