FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 361

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.8
9.8.1
Intel
®
Table 9-8. PCI Configuration Map (PM—D31:F0)
82801DBM ICH4-M Datasheet
Power Management Registers (D31:F0)
The power management registers are distributed within the PCI Device 31: Function 0 space, as
well as a separate I/O range. Each register is described below. Unless otherwise indicate, bits are in
the main (core) power well.
Bits not explicitly defined in each register are assumed to be reserved. When writing to a reserved
bit, the value should always be 0. Software should not attempt to use the value read from a reserved
bit, as it may not be consistently 1 or 0.
Power Management PCI Configuration Registers (D31:F0)
Table 9-8
only those registers dedicated for power management. Some of the registers are only used for
Legacy Power management schemes.
C4–CAhh
40h
B8–BBh
Offset
CCh
44h
A0h
A2h
A4h
A8h
C0
–
43h
shows a small part of the configuration space for PCI Device 31: Function 0. It includes
MON[ n ]_TRP_RNG
MON_TRP_MSK
GEN_PMCON_1
GEN_PMCON_2
GEN_PMCON_3
TRP_FWD_EN
STPCLK_DEL
ACPI_CNTL
GPI_ROUT
Mnemonic
PM_BASE
ACPI Base Address (See
Section
ACPI Control (See
General Power Management
Configuration 1
General Power Management
Configuration 2
General Power Management
Configuration 3
Stop Clock Delay Register
GPI Route Control
I/O Monitor Trap Forwarding Enable
I/O Monitor[4:7] Trap Range
I/O Monitor Trap Range Mask
9.1.10)
Register Name
Section
LPC Interface Bridge Registers (D31:F0)
9.1.11)
00000001h
00000000h
Default
0000h
0000h
0000h
0000h
0Dh
00h
00h
R/WO, R/WC
R/WC, R/W
R/W, R/WC
R/W, RO,
Type
R/W
R/W
R/W
R/W
R/W
R/W
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