FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 277

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801DBM ICH4-M Datasheet
Bit
7:6
5:2
1:0
12
11
10
9
8
Receive Not Ready (RNR) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Interrupt signaled because the Receive Unit left the Ready state. This may be caused by an RU
Management Data Interrupt (MDI) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Set when a Management Data Interface read or write cycle has completed. The management
Software Interrupt (SWI) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Set when software generates an interrupt.
Early Receive ( ER ) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Indicates the occurrence of an Early Receive Interrupt.
Flow Control Pause ( FCP ) — R/WC.
0 = Software acknowledges the interrupt and clears this bit by writing a 1 to the bit position.
1 = Indicates Flow Control Pause interrupt.
Command Unit Status (CUS) — RO.
00 = Idle
01 = Suspended
10 = LPQ (Low Priority Queue) active
11 = HPQ (High Priority Queue) active
Receive Unit Status (RUS) —RO.
0000 = Idle1000 = Reserved
0001 = Suspended1001 = Suspended with no more RBDs
0010 = No Resources1010 = No resources due to no more RBDs
0011 = Reserved1011 = Reserved
0100 = Ready1100 = Ready with no RBDs present
0101 = Reserved1101 = Reserved
0110 = Reserved1110 = Reserved
0111 = Reserved1111 = Reserved
Reserved
Abort command, a no resources situation, or set suspend bit due to a filled Receive Frame
Descriptor.
data interrupt is enabled through the interrupt enable bit (bit 29 in the Management Data
Interface Control register in the CSR).
Description
LAN Controller Registers (B1:D8:F0)
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