FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 216

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.17.7.4
5.17.7.5
5.17.8
216
ACPI System States
The EHC behavior as it relates to other power management states in the system is summarized in
the following list:
Mobile Considerations
The ICH4 USB EHCI implementation does not behave differently in the mobile configurations
versus the desktop configurations. However, some features may be especially useful for the mobile
configurations.
Interaction with Classic Host Controllers
The Enhanced Host Controller shares the 6 USB ports with 3 UHCI Host Controllers in the ICH4.
The USB UHCI Controller at D29:F0 shares ports 0 and 1; the USB UHCI Controller at D29:F1
shares ports 2 and 3; and the USB UHCI Controller at D29:F2 shares ports 4 and 5 with the EHCI
Controller. There is very little interaction between the USB EHCI and the USB UHCI controllers
other than the muxing control which is provided as part of the EHCI Controller.
Figure 5-20
indicates all of the logic that is part of the Enhanced Host Controller cluster.
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The System is always in the S0 state when the EHC is in the D0 state. However, when the
EHC is in the D3 state, the system may be in any power management state (including S0).
When in D0, the Pause feature (See
states to be entered.
The PLL in the EHC is disabled when entering the S1-M state (48 MHz clock stops), or the
S3/S4/S5 states (core power turns off).
All core well logic is reset in the S3/S4/S5 states (core power turns off).
Mobile systems are not likely to use all 6 of the USB ports that are provided on the ICH4. With
this in mind, the ICH4 provides mechanisms for changing the structural parameters of the
EHC and hiding unused USB UHCI controllers. See ICH4 BIOS Specification on how BIOS
should configure the ICH4.
Mobile systems may want to minimize the conditions that will wake the system. The ICH4
implements the “Wake Enable” bits in the Port Status and Control registers, as specified in the
EHCI specification, for this purpose.
Mobile systems may want to cut suspend well power to some or all USB ports when in a low-
power state. The ICH4 implements the optional Port Wake Capability Register in the EHC
Configuration Space for this platform-specific information to be communicated to software.
depicts the USB Port Connections at a conceptual level. The dashed rectangle
Section
5.17.7.1) enables dynamic processor low-power
Intel
®
82801DBM ICH4-M Datasheet