FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 377

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.8.3.10
Intel
®
82801DBM ICH4-M Datasheet
Note: This register is symmetrical to the General Purpose Event 0 Enable Register. If the corresponding
GPE0_STS—General Purpose Event 0 Status Register
I/O Address:
Default Value:
Lockable:
Power Well:
_EN bit is set, then when the _STS bit gets set, the ICH4 generates a Wake Event. Once back in an
S0 state (or if already in an S0 state when the event occurs), the ICH4 also generates an SCI if the
SCI_EN bit is set, or an SMI# if the SCI_EN bit is not set. There is no SCI/SMI# or wake event on
THRMOR_STS since there is no corresponding _EN bit. None of these bits are reset by CF9h
write. All are reset by RSMRST#.
31:16
15:14
Bit
13
12
10
11
9
8
GPIn_STS — R/WC. These bits are set any time the corresponding GPIO is set up as an input
and the corresponding GPIO signal is high (or low if the corresponding GP_INV bit is set). If the
corresponding enable bit is set in the GPE0_EN register, then when the GPI[n]_STS bit is set:
Reserved
PME_B0_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position. (default)
1 = This bit will be set to 1 by the ICH4 when any internal device on bus 0 asserts the equivalent
USB3_STS — R/W
0 = Disable.
1 = Set by hardware and can be reset by writing a one to this bit position or a resume-well reset.
PME_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the PME# signal goes active. Additionally, if the PME_EN bit is set,
BATLOW_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the BATLOW# signal is asserted.
Global Standby Timer Status ( GST_STS) — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware to indicate that the wake event was due to GST timeout. This bit will only be
RI_STS — R/WC.
0 = Software clears this bit by writing a 1 to the bit position.
1 = Set by hardware when the RI# input signal goes active.
• If the system is in an S1-M–S5 state, the event will also wake the system.
• If the system is in an S0 state (or upon waking back to an S0 state), a SCI will be caused
depending on the GPI_ROUT bits for the corresponding GPI.
of the PME# signal. Additionally, if the PME_B0_EN bit is set, and the system is in an S0
state, then the setting of the PME_B0_STS bit will generate an SCI (or SMI# if SCI_EN is not
set). If the PME_B0_STS bit is set, and the system is in an S1-M–S4 state (or S5 state due to
SLP_TYP and SLP_EN), then the setting of the PME_B0_STS bit will generate a wake
event, and an SCI (or SMI# if SCI_EN is not set) will be generated. If the system is in an S5
state due to power button override, then the PME_B0_STS bit will not cause a wake event or
SCI.
This bit is set when USB UHCI Controller #3 needs to cause a wake. Additionally if the
USB3_EN bit is set, the setting of the USB3_STS bit will generate a wake event.
and the system is in an S0 state, then the setting of the PME_STS bit will generate an SCI or
SMI# (if SCI_EN is not set). If the PME_EN bit is set, and the system is in an S1-M–S4 state
(or S5 state due to setting SLP_TYP and SLP_EN), then the setting of the PME_STS bit will
generate a wake event, and an SCI will be generated. If the system is in an S5 state due to
power button override or a power failure, then PME_STS will not cause a wake event or SCI.
set when the system was in the S1-M state.
PMBASE + 28h
(
00000000h
No
Resume
ACPI GPE0_BLK )
Description
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
R/WC, R/W
32 bit
ACPI
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