FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 407

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

10.1.15
10.1.16
10.1.17
Intel
®
82801DBM ICH4-M Datasheet
Note: This is a memory mapped BAR that requires 1 KB of DWord-aligned memory that is Intel reserved
EXBAR — Expansion Base Address Register (IDE—D31:F1)
Address Offset:
Default Value:
for future functionality. BIOS needs to program the base address for a 1-kB memory space.
IDE_SVID — Subsystem Vendor ID Register (IDE—D31:F1)
Address Offset:
Default Value:
Lockable:
IDE_SID — Subsystem ID Register (IDE—D31:F1)
Address Offset:
Default Value:
Lockable:
15:0
15:0
31:0
Bit
Bit
Bit
Subsystem Vendor ID (SVID) — R/Write-Once. The SVID register, in combination with the
Subsystem ID (SID) register, enables the operating system (OS) to distinguish subsystems from
each other. Software (BIOS) sets the value in this register. After that, the value can be read, but
subsequent writes to this register have no effect. The value written to this register will also be
readable via the corresponding SVID registers for the USB UHCI #1, USB UHCI #2, USB UHCI #3,
and SMBus functions.
Subsystem ID (SID) — R/Write-Once. The SID register, in combination with the SVID register,
enables the operating system (OS) to distinguish subsystems from each other. Software (BIOS)
sets the value in this register. After that, the value can be read, but subsequent writes to this register
have no effect. The value written to this register will also be readable via the corresponding SID
registers for the USB UHCI #1, USB UHCI #2, USB UHCI #3, and SMBus functions.
Intel Reserved for Future Functionality.
24h
00h
2Ch
00h
No
2Eh
00h
No
–
–
–
27h
2Fh
2Dh
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Power Well: Core
Attribute:
Size:
Power Well: Core
IDE Controller Registers (D31:F1)
R/W
32 bits
R/WO
16 bits
R/WO
16 bits
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