FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 123

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 5-21. Short Message
82801DBM ICH4-M Datasheet
Short Message
Short messages are used for the delivery of Fixed, NMI, SMI, Reset, ExtINT, and Lowest Priority
with Focus processor interrupts. The Delivery Mode bits (M2–M0) specify the message. All short
messages take 21 cycles including the idle cycle.
NOTES:
1. If DM is 0 (physical mode), cycles 15 and 16 are the APIC ID and cycles 13 and 14 are sent as 1. If DM is 1
2. The checksum field is the cumulative add (mod 4) of all data bits (DM, M0–3, L, TM, V0–7, D0–7). The APIC
3. This cycle allows all APICs to perform various internal computations based on the information contained in
Cycle
(logical mode), cycles 13 through 16 are the 8-bit Destination field. The interpretation of the logical mode 8-bit
Destination field is performed by the local units using the Destination Format Register. Shorthands of “all-incl-
self” and “all-excl-self” both use physical destination mode and a destination field containing APIC ID value of
all ones. The sending APIC knows whether it should (incl) or should not (excl) respond to its own message.
driving the message provides this checksum. This, in essence, is the lower two bits of an adder at the end of
the message.
the received message. One of the computations takes the checksum of the data received in cycles 6 through
16 and compares it with the value in cycle 18. If any APIC computes a different checksum than the one
passed in cycle 17, then that APIC will signal an error on the APIC bus (“00”) in cycle 19. If this happens, all
APICs will assume the message was never sent and the sender must try sending the message again, which
includes re-arbitrating for the APIC bus. In lowest priority delivery when the interrupt has a focus processor,
the focus processor will signal this by driving a 01 during cycle 19. This tells all the other APICs that the
interrupt has been accepted, the arbitration is preempted, and short message format is used. Cycle 19 and
20 indicates the status of the message (i.e., accepted, check sum error, retry, or error).
status signal combinations and their meanings for all delivery modes.
2–5
10
12
13
14
15
16
17
18
19
20
21
11
1
6
7
8
9
NOT(DM)
NOT(M1)
NOT(V7)
NOT(V5)
NOT(V3)
NOT(V1)
NOT(D7)
NOT(D5)
NOT(D3)
NOT(D1)
NOT(C1)
NOT(A1)
NOT(A)
NOT(L)
ARBID
Bit 1
1
1
1
NOT(M2)
NOT(M0)
NOT(TM)
NOT(V6)
NOT(V4)
NOT(V2)
NOT(V0)
NOT(D6)
NOT(D4)
NOT(D2)
NOT(D0)
NOT(C0)
NOT(A1)
NOT(A)
Bit 0
0
1
1
1
Normal Arbitration
Arbitration ID
DM
register
M2-M0 = Delivery Mode from bits 10:8 of the redirection table
register
L = Level, TM = Trigger Mode
Interrupt vector bits V7 - V0 from redirection table register
Destination field from bits 63:56 of redirection table register
Checksum for Cycles 6–16
Postamble
Status Cycle 0. See
Status Cycle 1. See
Idle
1
= Destination Mode from bit 11 of the redirection table
3
Table
Table
Comments
5-22.
5-22.
2
Functional Description
Table 5-22
shows the
1
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