FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 188

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
188
Table 5-58. TD Control and Status (Sheet 1 of 2)
31:30
28:27
Bit
29
26
25
24
23
Reserved.
Short Packet Detect (SPD). When a packet has this bit set to 1 and the packet is an input packet, is
in a queue; and successfully completes with an actual length less than the maximum length, then
the TD is marked inactive, the Queue Header is not updated, and the USBINT status bit (Status
Register) is set at the end of the frame. In addition, if the interrupt is enabled, the interrupt will be
sent at the end of the frame.
Note that any error (e.g., babble or FIFO error) prevents the short packet from being reported. The
behavior is undefined when this bit is set with output packets or packets outside of queues.
0 = Disable
1 = Enable
Error Counter (C_ERR). This field is a 2-bit down counter that keeps track of the number of Errors
detected while executing this TD. If this field is programmed with a non zero value during setup, the
ICH4 decrements the count and writes it back to the TD if the transaction fails. If the counter counts
from one to zero, the ICH4 marks the TD inactive, sets the “STALLED” and error status bit for the
error that caused the transition to zero in the TD. An interrupt will be generated to Host Controller
Driver (HCD) if the decrement to zero was caused by Data Buffer error, Bit stuff error, or if enabled,
a CRC or Timeout error. If HCD programs this field to zero during setup, the ICH4 will not count
errors for this TD and there will be no limit on the retries of this TD.
Bits[28:27]Interrupt After
00 No Error Limit
01 1 Error
10 2 Errors
11 3 Errors
Error Decrement Counter Error Decrement Counter
CRC ErrorYesData Buffer ErrorYes
Timeout ErrorYesStalledNo
NAK ReceivedNoBit stuff ErrorYes
Babble DetectedNo
NOTE 1. Detection of Babble or Stall automatically deactivates the TD. Thus, count is not
Low Speed Device (LS). This bit indicates that the target device (USB data source or sink) is a low
speed device, running at 1.5 Mb/s, instead of at full speed (12 Mb/sec). There are special
restrictions on schedule placement for low speed TDs. If an ICH4 root hub port is connected to a full
speed device and this bit is set to a 1 for a low speed transaction, the ICH4 sends out a low speed
preamble on that port before sending the PID. No preamble is sent if an ICH4 root hub port is
connected to a low speed device.
0 = Full Speed Device
1 = Low Speed Device
Isochronous Select (IOS). The field specifies the type of the data structure. If this bit is set to a 1,
the TD is an isochronous transfer. Isochronous TDs are always marked inactive by the hardware
after execution, regardless of the results of the transaction.
0 = Non-isochronous Transfer Descriptor
1 = Isochronous Transfer Descriptor
Interrupt on Complete (IOC). This specifies that the ICH4 should issue an interrupt on completion
of the frame in which this Transfer Descriptor is executed. Even if the Active bit in the TD is already
cleared when the TD is fetched (no transaction will occur on USB), an IOC interrupt is generated at
the end of the frame.
1 = Issue IOC
Active. For ICH4 schedule execution operations, see
Memory.
0 = When the transaction associated with this descriptor is completed, the ICH4 sets this bit to 0
1 = Set to 1 by software to enable the execution of a message transaction by the ICH4.
indicating that the descriptor should not be executed when it is next encountered in the
schedule. The Active bit is also set to 0 if a stall handshake is received from the endpoint.
decremented.
1
1
Description
Section
Intel
5.16.2, Data Transfers to/from Main
®
82801DBM ICH4-M Datasheet