FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 283

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

7.2.7
7.2.8
Intel
®
82801DBM ICH4-M Datasheet
Note: It is recommended that software not utilize this register unless receive interrupt latency is a critical
Receive DMA Byte Count Register
Offset Address:
Default Value:
Early Receive Interrupt Register
Offset Address:
Default Value:
The Early Receive Interrupt register allows the internal LAN Controller to generate an early
interrupt depending on the length of the frame. The LAN Controller will generate an interrupt at
the end of the frame regardless of whether or not Early Receive Interrupts are enabled.
performance issue in that particular software environment. Using this feature may reduce receive
interrupt latency, but will also result in the generation of more interrupts, that can degrade system
efficiency and performance in some environments.
31:0
7:0
Bit
Bit
Receive DMA Byte Count — RO. Keeps track of how many bytes of receive data have been
passed into host memory via DMA.
Early Receive Count — R/W. When some non-zero value x is programmed into this register, the
LAN controller will set the ER bit in the SCB Status Word Register and assert INTA# when the byte
count indicates that there are x quad-words remaining to be received in the current frame (based on
the Type/Length field of the received frame). No Early Receive interrupt will be generated if a value
of 00h (the default value) is programmed into this register.
14
0000 0000h
18h
00h
–
17h
Description
Description
Attribute:
Size:
Attribute:
Size:
LAN Controller Registers (B1:D8:F0)
RO
32 bits
R/W
8 bits
283