FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 443

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

12.1.13
12.1.14
12.1.15
12.1.16
Intel
®
82801DBM ICH4-M Datasheet
CAP_PTR—Capabilities Pointer Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
INT_LN—Interrupt Line Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
INT_PN—Interrupt Pin Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
PWR_CAPID—PCI Power Management Capability ID
Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
7: 0
7:0
7:0
7:0
Bit
Bit
Bit
Bit
Capabilities Pointer (CAP_PTR) — RO. This register points to the starting offset of the USB EHCI
capabilities ranges.
Interrupt Line (INT_LN) — R/W. This data is not used by the ICH4. It is used as a scratchpad
register to communicate to software the interrupt line that the interrupt pin is connected to.
Interrupt Pin (INT_PN) — RO. The value of 04h indicates that the USB EHCI function within the
ICH4’s multi-function USB device will drive the fourth interrupt pin from the device (INTD# in PCI
terms). The value of 04h in function 7 is required because the PCI specification does not recognize
more than 4 interrupts and older APM-based OSs require that each function within a multi-function
device has a different Interrupt Pin Register value.
NOTE: Internally the USB EHCI controller uses PIRQ[H]#.
Power Management Capability ID — RO. A value of 01h indicates that this is a PCI Power
Management capabilities field.
34h
50h
3Ch
00h
3Dh
04h
50h
01h
Description
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
EHCI Controller Registers (D29:F7)
RO
8 bits
R/W
8 bits
RO
8 bits
RO
8 bits
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