FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 174

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.14.2
5.14.3
174
Table 5-50. GPIO Implementation (Sheet 2 of 2)
NOTES:
Power Wells
Some GPIOs exist in the resume power plane. Care must be taken to make sure GPIO signals are
not driven high into powered-down planes.
Some ICH4 GPIOs may be connected to pins on devices that exist in the core well. If these GPIOs
are outputs, there is a danger that a loss of core power (PWROK low) or a Power Button Override
event will result in the ICH4 driving a pin to a logic 1 to another device that is powered down.
GPIO[1:15] have “sticky” bits on the input. Refer to the GPE0_STS register. As long as the signal
goes active for at least 2 clocks, the ICH4 will keep the sticky status bit active. The active level can
be selected in the GP_LVL register.
If the system is in an S0 state, the GPI inputs are sampled at 33 MHz, so the signal only needs to be
active for about 60 ns to be latched. In the S1-M or S3–S5 states, the GPI inputs are sampled at
32.768 kHz, and thus must be active for at least 61 microseconds to be latched.
If the input signal is still active when the latch is cleared, it will again be set. Another edge trigger
is not required. This makes these signals “level” triggered inputs.
SMI# and SCI Routing
The routing bits for GPIO[0:15] allow an input to be routed to SMI# or SCI, or neither. Note that a
bit can be routed to either an SMI# or an SCI, but not both.
1. All GPIOs default to their alternate function.
2. All inputs are sticky. The status bit remains set as long as the input was asserted for 2 clocks. GPIs are
3. GPIO[0:7] are 5 V tolerant, and all GPIs can be routed to cause an SCI or SMI#.
4. If GPIO_USE_SEL bit 1 is set to 1 and GEN_CNT bit 25 is also set to 1 then REQ/GNT[5]# is enabled. See
GPIO[18:24]
GPIO[27:28]
GPIO[29:31]
GPIO[43:32]
GPIO[25]
GPIO[26]
GPO[17]
sampled on PCI clocks in S0. GPIs are sampled on RTC clocks in and S1-M/S3/S4/S5.
Section
GPIO
9.1.22.
Output
Type
Only
N/A
N/A
N/A
I/O
I/O
I/O
Function
GNT[B]# or
Alternate
Unmuxed
Unmuxed
Unmuxed
GNT[5]#
N/A
N/A
N/A
(1)
Resume
Resume
Power
Core
Core
Well
N/A
N/A
N/A
Tolerant
3.3 V
3.3 V
3.3 V
3.3 V
• Output controlled via GP_LVL register
• TTL driver output
• Not implemented
• Blink enabled via GPO_BLINK register
• Input active status read from GP_LVL
• Output controlled via GP_LVL register
• TTL driver output
• Not implemented
• Input active status read from GP_LVL
• Output controlled via GP_LVL register
• TTL driver output
• Not implemented
Intel
bit 17.
bit 25.
register bit 25
bit 25.
register bits [27:28]
bits [27:28]
®
82801DBM ICH4-M Datasheet
Notes