FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 93

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.3.1.1
5.3.1.2
Intel
®
Table 5-2. LPC Cycle Types Supported
Table 5-3. Start Field Bit Definitions
82801DBM ICH4-M Datasheet
LPC Cycle Types
The ICH4 implements all of the cycle types described in the Low Pin Count Interface
Specification, Revision 1.0.
NOTES:
Start Field Definition
NOTE: All other encodings are RESERVED.
1. For memory cycles below 16 MB which do not target enabled FWH ranges, the ICH4 performs standard LPC
2. Bus Master Read or Write cycles must be naturally aligned. For example, a 1-byte transfer can be to any
Encoding
Bits[3:0]
memory cycles. It only attempts 8-bit transfers. If the cycle appears on PCI as a 16-bit transfer, it will appear
as two consecutive 8-bit transfers on LPC. Likewise, if the cycle appears as a 32-bit transfer on PCI, it will
appear as four consecutive 8-bit transfers on LPC. If the cycle is not claimed by any peripheral, it will be
subsequently aborted, and the ICH4 will return a value of all 1s to the processor. This is done to maintain
compatibility with ISA memory cycles where pull-up resistors would keep the bus high if no device responds.
address. However, the 2-byte transfer must be word aligned (i.e., with an address where A0=0). A DWord
transfer must be DWord aligned (i.e., with an address where A1and A0 are both 0).
Bus Master Read
Bus Master Write
0000
0010
0011
1111
Memory Read
Memory Write
Cycle Type
DMA Read
DMA Write
I/O Read
I/O Write
Start of cycle for a generic target
Grant for bus master 0
Grant for bus master 1
Stop/Abort: End of a cycle for a target.
Single: 1 byte only
Single: 1 byte only
1 byte only. ICH4 breaks up 16 and 32-bit processor cycles into multiple 8-bit
transfers. (See Note 1)
1 byte only. ICH4 breaks up 16 and 32-bit processor cycles into multiple 8-bit
transfers. (See Note 1)
Can be 1, or 2 bytes
Can be 1, or 2 bytes
Can be 1, 2, or 4 bytes. (See Note 2)
Can be 1, 2, or 4 bytes. (See Note 2)
Table 5-2
shows the cycle types supported by the ICH4.
Definition
Comment
Functional Description
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