FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 554

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Electrical Characteristics
554
Table 17-11. Ultra ATA Timing (Mode 0, Mode 1, Mode 2)
NOTES:
1. The specification symbols in parentheses correspond to the AT Attachment - 6 with Packet Interface
2. See the AT Attachment - 6 with Packet Interface (ATA/ATAPI - 6) Specification for further details on
Sym
t92b
t96a
t96b
t98a
t98b
t93
t94
t95
t97
t99
(ATA/ATAPI - 6) specification name.
measuring these timing parameters.
CRC word valid hold time at
sender (from DMACK#
negation until CRC may
become invalid) (see Note 2)
(Tcvh)
STROBE output released-to-
driving to the first transition
of critical timing (Tzfs)
Data Output Released-to-
Driving Until the First
Tunisian of Critical Timing
(Tdzfs)
Unlimited Interlock Time
(Tui)
Maximum time allowed for
output drivers to release
(from asserted or negated)
(Taz)
Minimum time for drivers to
assert or negate (from
released) (Tzad)
Ready-to-final-STROBE time
(no STROBE edges shall be
sent this long after negation
of DMARDY#) (Trfs)
Maximum time before
releasing IORDY (Tiordyz)
Minimum time before driving
IORDY (see Note 2)
(Tziordy)
Time from STROBE edge to
negation of DMARQ or
assertion of STOP (when
sender terminates a burst)
(Tss)
Parameter (1)
Mode 0 (ns)
Min
6.2
70
50
0
0
0
0
Max
10
75
20
Mode 1 (ns)
Min
6.2
48
50
0
0
0
0
Max
10
70
20
Intel
Mode 2 (ns)
Min
6.2
31
50
0
0
0
0
®
82801DBM ICH4-M Datasheet
Max
10
60
20
Host
Connector
Device
Connector
Sender
Connector
Host
Connector
See Note 2
Device
Connector
Sender
Connector
Device
Connector
Device
Connector
Sender
Connector
Measuring
Location
Figure