FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 355

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.6.2.1
Intel
®
82801DBM ICH4-M Datasheet
RTC_REGA—Register A
RTC Index:
Default Value:
Lockable:
This register is used for general configuration of the RTC functions. None of the bits are affected
by RSMRST# or any other ICH4 reset signal.
Bit
6:4
3:0
7
Update In Progress (UIP) — R/W. This bit may be monitored as a status flag.
0 = The update cycle will not start for at least 492 µs. The time, calendar, and alarm information in
1 = The update is soon to occur or is in progress.
Division Chain Select (DV[2:0]) — R/W. These three bits control the divider chain for the oscillator,
and are not affected by RSMRST# or any other reset signal. DV[2] corresponds to bit 6.
010 = Normal Operation
11X = Divider Reset
101 = Bypass 15 stages (test mode only)
100 = Bypass 10 stages (test mode only)
011 = Bypass 5 stages (test mode only)
001 = Invalid
000 = Invalid
Rate Select (RS[3:0]) — R/W. Selects one of 13 taps of the 15 stage divider chain. The selected tap
can generate a periodic interrupt if the PIE bit is set in Register B. Otherwise this tap will set the PF
flag of Register C. If the periodic interrupt is not to be used, these bits should all be set to zero. RS3
corresponds to bit 3.
0000 = Interrupt never toggles
0001 = 3.90625 ms
0010 = 7.8125 ms
0011 = 122.070 µs
0100 = 244.141 µs
0101 = 488.281 µs
0110 = 976.5625 µs
0111 = 1.953125 ms
1000 = 3.90625 ms
1001 = 7.8125 ms
1010 = 15.625 ms
1011 = 31.25 ms
1100 = 62.5 ms
1101 = 125 ms
1110 = 250 ms
1111= 500 ms
RAM is always available when the UIP bit is 0.
0A
Undefined
No
Description
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
R/W
8 bit
RTC
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