FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 457

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

12.2.2.1
Intel
®
82801DBM ICH4-M Datasheet
EHCI_CMD—USB EHCI Command Register
Offset:
Default Value:
31:24
23:16
15:8
11:8
3:2
Bit
7
6
5
4
Reserved. Should be set to 0s.
Interrupt Threshold Control  R/W. This field is used by system software to select the maximum
rate at which the host controller will issue interrupts. The only valid values are defined below. If
software writes an invalid value to this register, the results are undefined.
00h = Reserved
01h = 1 micro-frame
02h = 2 micro-frames
04h = 4 micro-frames
08h = 8 micro-frames (default, equates to 1 ms)
10h = 16 micro-frames (2 ms)
20h = 32 micro-frames (4 ms)
40h = 64 micro-frames (8 ms)
Reserved. Should be set to 0s.
Unimplemented Asynchronous Park Mode Bits — RO. Hardwired to 000b; the host controller does
not support this optional feature.
Light Host Controller Reset — RO. Hardwired to 0; the ICH4 does not implement this optional reset.
Interrupt on Async Advance Doorbell — R/W. This bit is used as a doorbell by software to tell the
host controller to issue an interrupt the next time it advances asynchronous schedule.
0 = The host controller sets this bit to a 0 after it has set the Interrupt on Async Advance status bit in
1 = Software must write a 1 to this bit to ring the doorbell. When the host controller has evicted all
Asynchronous Schedule Enable  R/W. This bit controls whether the host controller skips
processing the Asynchronous Schedule.
0 = Do not process the Asynchronous Schedule (Default)
1 = Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
Periodic Schedule Enable  R/W. This bit controls whether the host controller skips processing
the Periodic Schedule.
0 = Do not process the Periodic Schedule (Default)
1 = Use the PERIODICLISTBASE register to access the Periodic Schedule.
Frame List Size  RO. Hardwired to 00; ICH4 only supports the 1024-element frame list size.
the EHCI_STS register to a 1.
appropriate cached schedule state, it sets the Interrupt on Async Advance status bit in the
EHCI_STS register. If the Interrupt on Async Advance Enable bit in the USBINTR register is a 1
then the host controller will assert an interrupt at the next interrupt threshold. See the Enhanced
Host Controller Interface (EHCI) Specification for Universal Serial Bus for operational details.
Software should not write a 1 to this bit when the asynchronous schedule is inactive. Doing this
will yield undefined results.
CAPLENGTH + 00
00080000h
–
03h
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W, RO
32 bits
457