FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 8

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

8
5.9
5.10
5.11
5.12
5.8.5
Serial Interrupt (D31:F0) .............................................................................. 130
5.9.1
5.9.2
5.9.3
5.9.4
5.9.5
Real Time Clock (D31:F0) ........................................................................... 133
5.10.1 Update Cycles ................................................................................ 133
5.10.2 Interrupts......................................................................................... 134
5.10.3 Lockable RAM Ranges ................................................................... 134
5.10.4 Century Rollover ............................................................................. 134
5.10.5 Clearing Battery-Backed RTC RAM................................................ 134
Processor Interface (D31:F0) ...................................................................... 136
5.11.1 Processor Interface Signals ............................................................ 136
5.11.2 Speed Strapping for Processor....................................................... 139
Power Management (D31:F0) ..................................................................... 140
5.12.1 Intel
5.12.2 System Power Planes..................................................................... 143
5.12.3 Intel
5.12.4 SMI#/SCI Generation...................................................................... 143
5.12.5 Dynamic Processor Clock Control .................................................. 145
5.12.6 Dynamic PCI Clock Control ............................................................ 148
5.12.7 Sleep States ................................................................................... 150
5.12.8 Thermal Management..................................................................... 154
5.8.4.1
5.8.4.2
Processor System Bus Interrupt Delivery ....................................... 128
5.8.5.1
5.8.5.2
5.8.5.3
5.8.5.4
5.8.5.5
Start Frame ..................................................................................... 131
Data Frames ................................................................................... 131
Stop Frame ..................................................................................... 131
Specific Interrupts Not Supported via SERIRQ............................... 132
Data Frame Format ........................................................................ 132
5.11.1.1 A20M# ............................................................................. 136
5.11.1.2 INIT#................................................................................ 136
5.11.1.3 FERR#/IGNNE# (Coprocessor Error) ............................. 137
5.11.1.4 NMI.................................................................................. 138
5.11.1.5 STPCLK# and CPUSLP# Signals ................................... 138
5.11.1.6 CPUPWRGOOD Signal .................................................. 138
5.11.1.7 DPSLP#........................................................................... 138
5.12.5.1 Throttling Using STPCLK# .............................................. 147
5.12.5.2 Transition Rules among S0/Cx and Throttling States ..... 147
5.12.6.1 Conditions for Stopping the PCI Clock ............................ 148
5.12.6.2 Conditions for Maintaining the PCI Clock........................ 148
5.12.6.3 Conditions for Stopping the PCI Clock ............................ 149
5.12.6.4 Conditions for Re-Starting the PCI Clock ........................ 149
5.12.6.5 Other Causes of CLKRUN# Going Active ....................... 149
5.12.6.6 LPC Devices and CLKRUN#........................................... 150
5.12.7.1 Sleep State Overview...................................................... 150
5.12.7.2 Initiating Sleep State ....................................................... 151
5.12.7.3 Exiting Sleep States ........................................................ 151
5.12.7.4 Sx-G3-Sx, Handling Power Failures................................ 153
5.12.8.1 THRM# Signal ................................................................. 154
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ICH4 and System Power States ........................................... 141
ICH4 Power Planes............................................................... 143
Theory of Operation ........................................................ 127
Registers and Bits Associated with PCI Interrupt Delivery128
Theory of Operation ........................................................ 128
Edge-Triggered Operation............................................... 128
Level-Triggered Operation .............................................. 128
Registers Associated with Processor System Bus
Interrupt Delivery ............................................................. 129
Interrupt Message Format ............................................... 129
Intel
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82801DBM ICH4-M Datasheet