FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 86

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.2.2.3
5.2.2.4
86
CLOCKRUN# Signal
The ICH4 receives a free-running 33-MHz clock. It does not stop based on the CLKRUN# signal
and protocol. When the LAN controller runs cycles on the PCI bus, the ICH4 makes sure that the
STP_PCI# signal is high indicating that the PCI clock will be running. This is to make sure that any
PCI tracker does not get confused by transactions on the PCI bus with its PCI clock stopped.
PCI Power Management
Enhanced support for the power management standard, PCI Local Bus Specification, Revision 2.2,
is provided in the ICH4 integrated LAN Controller. The LAN Controller supports a large set of
wake-up packets and the capability to wake the system from a low power state on a link status
change. The LAN Controller enables the host system to be in a sleep state and remain virtually
connected to the network.
After a power management event or link status change is detected, the LAN Controller will wake
the host system. The sections below describe these events, the LAN Controller power states, and
estimated power consumption at each power state.
Power States
The LAN Controller contains power management registers for PCI, and implements all four power
states as defined in the Power Management Network Device Class Reference Specification,
Revision 1.0. The four states (D0 through D3) vary from maximum power consumption at D0 to
the minimum power consumption at D3. PCI transactions are only allowed in the D0 state, except
for host accesses to the LAN Controller’s PCI configuration registers. The D1 and D2 power
management states enable intermediate power savings while providing the system wake-up
capabilities. In the D3 cold state, the LAN Controller can provide wake-up capabilities. Wake-up
indications from the LAN Controller are provided by the Power Management Event (PME#)
signal.
•
D0 Power State
As defined in the Network Device Class Reference Specification, the device is fully functional
in the D0 power state. In this state, the LAN Controller receives full power and should be
providing full functionality. In the LAN Controller the D0 state is partitioned into two
substates, D0 Uninitialized (D0u) and D0 Active (D0a).
D0u is the LAN Controller’s initial power state following a PCI RST#. While in the D0u state,
the LAN Controller has PCI slave functionality to support its initialization by the host and
supports Wake on LAN mode. Initialization of the CSR, Memory, or I/O Base Address
Registers in the PCI Configuration space switches the LAN Controller from the D0u state to
the D0a state.
In the D0a state, the LAN Controller provides its full functionality and consumes its nominal
power. In addition, the LAN Controller supports wake on link status change (see
Section
other words, a clock frequency greater than 16 MHz) for proper operation. The LAN
Controller supports a dynamic standby mode. In this mode, the LAN Controller is able to save
almost as much power as it does in the static power-down states. The transition to or from
standby is done dynamically by the LAN Controller and is transparent to the software.
5.2.2.6). While it is active, the LAN Controller requires a nominal PCI clock signal (in
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82801DBM ICH4-M Datasheet