FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 564

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Electrical Characteristics
564
Table 17-20. Power Management Timings (Sheet 2 of 2)
NOTES:
1. These transitions are clocked off the internal RTC. 1 RTC clock is approximately 32 µs.
2. This transition is clocked off the 66 MHz CLK66. 1 CLK66 is approximately 15 ns.
3. The ICH4 STPCLK# assertion will trigger the processor to send a stop grant acknowledge cycle. The timing
4. These transitions are clocked off the 33 MHz PCICLK. 1 PCICLK is approximately 30 ns.
5. The ICH4 has no maximum timing requirement for this transition. It is up to the system designer to determine
6. If the transition to S5 is due to Power Button Override, SLP_S3#, SLP_S4# and SLP_S5# are asserted
7. If there is no RTC battery in the system, so VccRTC and the VccSus supplies come up together, the delay
t198e SLP_S4# inactive to SLP_S3# inactive
Sym
t199
t200
t201
t203
t204
t205
t206
t207
t208
t209
t210
t212
t213
t214
t215
t216
t217
t218
t219
t220
t211
for this cycle getting to the ICH4 is dependant on the processor and the memory controller.
if the SLP_S3#, SLP_S4# and SLP_S5# signals are used to control the power planes.
together similar to timing t194 (PCIRST# active to SLP_S3# active).
from RTCRST# and RSMRST# inactive to SUSCLK toggling may be as much as 2.5 seconds.
SLP_S1# inactive to STP_CPU#, STP_PCI#
inactive
STP_CPU#, STP_PCI# inactive to SUS_STAT#
inactive
SUS_STAT# inactive to CPU_SLP# inactive
STPCLK# inactive to C3_STAT# inactive
CPU I/F signals latched prior to STPCLK# active
Break Event to STPCLK# inactive
STPCLK# inactive to processor I/F signals
unlatched
Break Event to STP_CPU# (for C3 exit) or
DPRSLPVR (for C4 exit) inactive
STP_CPU# and DPSLP# inactive to CPU_SLP#
inactive
DPSLP# active to DPRSLPVR active
DPRSLPVR inactive to DPSLP# inactive
SLP_S1# inactive to DPRSLPVR inactive
STP_CPU# to processor clock stopped Note: This is
a clock generator spec.
STP_CPU# inactive to processor clock running.
Note: This is a clock generator spec.
STP_CPU# active to SSMUXSEL transition.
DPSLP# active to start of VGATE ignore time.
VGATE ignore time after SSMUXSEL transition
(VGATE allowed to go high or low). VGATE must be
high at end of ignore time.
SSMUXSEL to STP_CPU# High
SLP_S1# to PCICLK stop
SLP_S1# inactive to PCICLK running
THRMTRIP# active to SLP_S3#, SLP_S4#,
SLP_S5# active
Parameter
Min
240
9.5
30
30
10
95
95
95
1
3
7
2
0
0
0
2
0
0
0
Max
Intel
312
188
101
101
101
200
6.2
1.8
10
15
45
13
—
11
2
4
4
0
0
8
3
3
0
2
®
RTCCLK
82801DBM ICH4-M Datasheet
PCI CLK
PCI CLK
PCI CLK
PCICLK
PCICLK
CLK66
Units
ms
ms
ms
ms
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
Notes
1
4
2
4
8
Figure
Figure
Figure
Figure
Figure
Figure
Figure 17-20
Figure 17-20
Figure 17-20
Figure 17-20
Figure 17-23
Figure 17-24
Figure 17-24
Figure 17-22
Figure 17-24
Figure 17-24
Figure 17-24
Figure 17-24
Figure 17-24
Figure 17-26
Figure 17-26
Figure 17-26
Figure 17-26
Figure 17-26
Figure 17-26
Figure 17-26
Figure 17-26
Fig
17-22,
17-23,
17-22,
17-23,
17-23,
17-23,