FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 28

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

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5-72
5-73
5-74
5-75
5-76
5-77
5-78
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5-80
5-81
5-82
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5-90
5-91
5-92
5-93
5-94
5-95
5-96
5-97
5-98
5-99
5-100 AC ’97 Signals ............................................................................................. 246
5-101 Input Slot 1 Bit Definitions............................................................................ 250
5-102 Output Tag Slot 0......................................................................................... 252
5-103 AC-link State during PCIRST#..................................................................... 255
6-1
6-2
6-3
6-4
7-1
7-2
7-3
7-4
7-5
7-6
8-1
9-1
9-2
9-3
9-4
9-5
9-6
SOF Packet ................................................................................................. 202
Data Packet Format ..................................................................................... 202
Bits Maintained in Low Power States .......................................................... 206
USB Legacy Keyboard State Transitions .................................................... 208
UHCI vs. EHCI............................................................................................. 209
Debug Port Behavior ................................................................................... 221
Quick Protocol ............................................................................................. 226
Send / Receive Byte Protocol without PEC ................................................. 226
Send/Receive Byte Protocol with PEC ........................................................ 227
Write Byte/Word Protocol without PEC........................................................ 227
Write Byte/Word Protocol with PEC............................................................. 228
Read Byte/Word Protocol without PEC ....................................................... 229
Read Byte/Word Protocol with PEC ............................................................ 229
Process Call Protocol without PEC.............................................................. 230
Process Call Protocol with PEC................................................................... 231
Block Read/Write Protocol without PEC ...................................................... 232
Block Read/Write Protocol with PEC ........................................................... 233
I
Enable for SMBALERT# .............................................................................. 236
Enables for SMBus Slave Write and SMBus Host Events........................... 236
Enables for the Host Notify Command ........................................................ 236
Slave Write Cycle Format ............................................................................ 238
Slave Write Registers .................................................................................. 238
Command Types ......................................................................................... 239
Read Cycle Format...................................................................................... 240
Data Values for Slave Read Registers ........................................................ 240
Host Notify Format ....................................................................................... 242
Features Supported by Intel
PCI Devices and Functions ......................................................................... 258
Fixed I/O Ranges Decoded by Intel
Variable I/O Decode Ranges ....................................................................... 262
Memory Decode Ranges from Processor Perspective ................................ 263
LAN Controller PCI Configuration Register Address Map
(LAN Controller—B1:D8:F0) ........................................................................ 265
Configuration of Subsystem ID and Subsystem Vendor ID via EEPROM ... 271
Data Register Structure ............................................................................... 275
Intel
Self-Test Results Format ............................................................................. 281
Statistical Counters...................................................................................... 287
Hub Interface PCI Configuration Register Address Map
(HUB-PCI—D30:F0) .................................................................................... 289
LPC I/F PCI Configuration Register Address Map (LPC I/F—D31:F0)........ 305
DMA Registers............................................................................................. 330
Interrupt Controller I/O Address Map (PIC Registers) ................................. 339
APIC Direct Registers .................................................................................. 347
APIC Indirect Registers ............................................................................... 347
RTC I/O Registers ....................................................................................... 353
2
C Block Read ............................................................................................ 234
®
ICH4 Integrated LAN Controller CSR Space ..................................... 276
®
ICH4 ............................................................. 243
®
ICH4.................................................. 260
Intel
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82801DBM ICH4-M Datasheet