FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 295

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

8.1.13
8.1.14
8.1.15
Intel
®
82801DBM ICH4-M Datasheet
SMLT—Secondary Master Latency Timer Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
This Master Latency Timer (MLT) controls the amount of time that the ICH4 will continue to burst
data as a master on the PCI bus. When the ICH4 starts the cycle after being granted the bus, the
counter is loaded and starts counting down from the assertion of FRAME#. If the internal grant to
this device is removed, then the expiration of the MLT counter will result in the deassertion of
FRAME#. If the internal grant has not been removed, then the ICH4 can continue to own the bus.
IOBASE—I/O Base Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
IOLIM—I/O Limit Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
Bit
7:3
2:0
Bit
7:4
3:0
Bit
7:4
3:0
Master Latency Timer Count (MLTC) — R/W. 5-bit value that indicates the number of PCI clocks,
in 8-clock increments, that the ICH4 will remain as master of the bus.
Reserved
I/O Address Base Bits [15:12] — R/W. I/O Base bits corresponding to address lines 15:12 for 4-
KB alignment. Bits 11:0 are assumed to be padded to 000h.
I/O Addressing Capability — RO. This is hardwired to 0h, indicating that the hub interface to PCI
bridge does not support 32-bit I/O addressing. This means that the I/O base & limit upper address
registers must be read only.
I/O Address Limit Bits [15:12] — R/W. I/O Base bits corresponding to address lines 15:12 for
4-KB alignment. Bits 11:0 are assumed to be padded to FFFh.
I/O Addressing Capability — RO. This is hardwired to 0h, indicating that the hub interface-to-PCI
bridge does not support 32-bit I/O addressing. This means that the I/O Base and I/O Limit Upper
Address registers must be read only.
1Bh
00h
1Ch
F0h
1Dh
00h
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
R/W
8 bits
R/W, RO
8 bits
R/W, RO
8 bits
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