FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 342

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.4.4
9.4.5
9.4.6
342
ICW3—Slave Controller Initialization Command Word 3
Register
Offset Address:
Default Value:
ICW4—Initialization Command Word 4 Register
Offset Address:
OCW1—Operational Control Word 1 (Interrupt Mask)
Register
Offset Address:
Default Value:
7:3
2:0
Bit
7:5
Bit
7:0
Bit
4
3
2
1
0
0 = These bits must be programmed to zero.
Slave Identification Code — WO. These bits are compared against the slave identification code
broadcast by the master controller from the trailing edge of the first internal INTA# pulse to the trailing
edge of the second internal INTA# pulse. These bits must be programmed to 02h to match the code
broadcast by the master controller. When 02h is broadcast by the master controller during the INTA#
sequence, the slave controller assumes responsibility for broadcasting the interrupt vector.
0 = These bits must be programmed to zero.
Special Fully Nested Mode (SFNM) — WO.
0 = Should normally be disabled by writing a 0 to this bit.
1 = Special fully nested mode is programmed.
Buffered Mode (BUF) — WO.
0 = Must be programmed to 0 for the ICH4. This is non-buffered mode.
Master/Slave in Buffered Mode — WO. Not used.
0 = Should always be programmed to 0.
Automatic End of Interrupt (AEOI) — WO.
0 = This bit should normally be programmed to 0. This is the normal end of interrupt.
1 = Automatic End of Interrupt (AEOI) mode is programmed.
Microprocessor Mode — WO.
1 = Must be programmed to 1 to indicate that the controller is operating in an Intel Architecture-
Interrupt Request Mask — R/W. When a 1 is written to any bit in this register, the corresponding
IRQ line is masked. When a 0 is written to any bit in this register, the corresponding IRQ mask bit is
cleared, and interrupt requests will again be accepted by the controller. Masking IRQ2 on the master
controller will also mask the interrupt requests from the slave controller.
based system.
Master Controller
Master Controller
00h
A1h
All bits undefined
Slave Controller
Slave Controller
–
–
0A1h
0A1h
–
–
021h
021h
Description
Description
Description
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
WO
8 bits
WO
8 bits
R/W
8 bits