FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 300

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Hub Interface to PCI Bridge Registers (D30:F0)
8.1.25
300
HI1_CMD—Hub Interface 1 Command Control Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
31:24
23:21
19:16
15:14
12:10
Bit
9:4
3:1
Bit
20
13
3
2
1
0
0
VGA Enable — R/W.
0 = No VGA device on PCI.
1 = Indicates that the VGA device is on PCI. Therefore, the PCI to hub interface decoder will not
ISA Enable — R/W. The ICH4 ignores this bit. However, this bit is read/write for software
compatibility. Since the ICH4 forwards all I/O cycles that are not in the USB, AC ’97, or IDE ranges to
PCI, this bit would have no effect.
SERR# Enable — R/W.
0 = Disable
1 = If this bit is set AND bit 8 in CMD register (D30:F0 Offset 04h) is also set, the ICH4 will set the
Parity Error Response Enable — R/W.
0 = Disable
1 = Enable the hub interface to PCI bridge for parity error detection and reporting on the PCI bus.
Reserved
Hub ID — RO. This field identifies the Hub Interface ID number for the Intel ICH4. The Intel ICH4 will
use this field for sending request packets from the Intel ICH4, and for routing completion packets back
from HI1.
Reserved
HI Timeslice — R/W. This field sets the HI arbiter time-slice value with 4 base-clock granularity. A
value of 0h means that the time-slice is immediately expired and that the ICH4 will allow the other
master’s request to be serviced after every message.
HI_Width — RO. This field is hardwired to 00b, indicating that the HI interface is 8 bits wide.
HI_Rate_Valid — RO. Hardwired to 1.
HI_Rate — RO. Encoded value representing the clock-to-transfer rate of the HI1 interface:
010 = 1:4
The value is loaded at reset by sampling the capability of the device connected to the HI1 port. The
value for this field is fixed for 4x mode only.
Reserved.
Max Data (MAXD) — RO. Hardwired to 001b. This field specifies the maximum amount of data that
the ICH4 is allowed to burst in one packet on the hub interface. The ICH4 will always do 64-byte
bursts.
Reserved
accept memory cycles in the range A0000h
cycles in the VGA range from PCI.
SSE bit in PD_STS register (D30:F0, offset 06h, bit 14) and also generate an NMI (or SMI# if
NMI routed to SMI) when the SERR# signal is asserted.
40–43h
00202802h
Description
Description
–
Attribute:
Size:
BFFFFh. Note that the ICH4 will never take I/O
Intel
®
82801DBM ICH4-M Datasheet
R/W, RO
32 bits