FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 261

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
Table 6-2. Fixed I/O Ranges Decoded by Intel
82801DBM ICH4-M Datasheet
NOTES:
1. Only if IDE Standard I/O space is enabled for Primary Channel and the IDE Controller is in legacy mode.
2. Only if IDE Standard I/O space is enabled for Secondary Channel and the IDE Controller is in legacy mode.
3. If POS_DEC_EN bit is enabled, reads from F0h will not be decoded by the ICH4. If POS_DEC_EN is not
I/O Address
4D0h–4D1h
1F0h–1F7h
170h–177h
Otherwise, the target is PCI.
Otherwise, the target is PCI.
enabled, reads from F0h will forward to LPC.
ACh–ADh
BCh–BDh
D2h–DDh
DEh–DFh
8Ch–8Eh
C0h–D1h
A0h–A1h
A4h–A5h
A8h–A9h
B0h–B1h
B2h–B3h
B4h–B5h
B8h–B9h
81h–83h
84h–86h
89h–8Bh
90h–91h
93h–9Fh
CF9h
08Fh
376h
3F6h
87h
88h
92h
F0h
Power Management
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Reset Generator
Reset Generator
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
IDE Controller
IDE Controller
IDE Controller
IDE Controller
Read Target
RESERVED
See Note 3
2
1
2
1
®
ICH4 (Sheet 2 of 2)
DMA Controller and LPC or PCI
DMA Controller and LPC or PCI
DMA Controller and LPC or PCI
FERR#/IGNNE# / Interrupt
Power Management
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Interrupt Controller
Reset Generator
Reset Generator
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
DMA Controller
IDE Controller
IDE Controller
IDE Controller
IDE Controller
Write Target
Controller
Register and Memory Mapping
2
1
2
1
Power Management
Forwarded to IDE
Forwarded to IDE
Forwarded to IDE
Forwarded IDE
Internal Unit
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
Interrupt
CPU I/F
CPU I/F
CPU I/F
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
DMA
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