FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 156

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.12.9.1
5.12.9.2
5.12.9.3
156
Intel SpeedStep Technology Processor Requirements
Processors without Intel SpeedStep technology use the A20M#, IGNNE#, NMI and INTR input
signals to determine the multiplier used by the processor’s PLL for the internal clock. With Intel
SpeedStep technology processors, two multiplier values (one for the Maximum Performance state,
a second for the Low Power-Battery Optimized state) are hard-wired within the processor. The
ICH4 CPUPERF signal is used to select the processor state, based on ICH4 control logic.
The operating bus ratio must be available to the programmer, and is therefore suggested that it be
read in a processor MSR. Also, the processor must return an indication that it is Intel SpeedStep
technology enabled, which should be in the form of a status bit in a processor MSR or in the
CPUID register.
The ICH4 is not capable of determining whether it is attached to a processor with or without Intel
SpeedStep technology. When used a processor without Intel SpeedStep technology, software
should not write or read the ICH4 Intel SpeedStep technology registers.
Intel SpeedStep Technology States
The ICH4 supports two system-level performance states: low-power mode and high-performance
mode. Processor states are defined by valid combinations of core voltage levels and core clock
speeds. These processor states can be used to alter the processor and system performance to
conform to conditions of power and environment.
The low-power mode is used primarily when the system is powered from the battery, with the
purpose being to maximize battery life. Mobile system performance is limited by thermal design
and battery capacity. To improve thermal capacity, active cooling solutions such as a fan can be
used, in addition to a passive cooling solution.
The high-performance mode assume that the mobile system is powered from an external AC/DC
source. The purpose of this state is to maximize performance subject to thermal constraints. The
ICH4 does not implement any restrictions on entry into high-performance mode. It will
unconditionally transition into high-performance mode upon software command.
Voltage Regulator Interface
The voltage regulator interface is critical to the Intel SpeedStep technology concept. The power
dissipation of the processor is proportional to the internal clock speed and to the square of the core
supply voltage. As the internal clock speed of the processor changes, the minimum required core
voltage supply level also changes. The interface signals are designed to allow the voltage regulator
to change settings without causing a power-on reset.
VGATE is an input from the regulator indicating that all of the outputs from the regulator are on
and within specification. When the system is transitioning between performance states, the voltage
regulator output may be required to change. It is not desirable, however, that CPUPWRGOOD
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VRCODE[4:0] is a 5-bit input to the Voltage Regulator. These signals are not outputs from the
ICH4, but instead are outputs from an external mux. Future voltage regulators may integrate
this mux.
The SSMUXSEL signal is an ICH4 output. It can be used directly can control the external mux
that selects the high or low values for VRCODE[4:0].
VRON (aka PWROK from main power supply) is an input to the regulator, and when VRON
is asserted the regulator turns on and settles to the output defined by VRCODE[4:0].
Intel
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82801DBM ICH4-M Datasheet