FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 426

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

USB UHCI Controllers Registers
11.1.17
426
USB_RES—USB Resume Enable Register
(USB—D29:F0/F1/F2)
Address Offset:
Default Value:
Bit
7:2
Bit
8
7
6
5
4
3
2
1
0
SMI Caused by Port 60 Read (TRAPBY60R) — R/WC. Indicates if the event occurred. Note that
even if the corresponding enable bit is not set in the bit 0, then this bit will still be active. It is up to the
SMM code to use the enable bit to determine the exact cause of the SMI#.
0 = Software clears this bit by writing a 1 to the bit location in any of the controllers.
1 = Event Occurred.
NOTE:This bit reports same value in all USB UHCI controllers.
SMI at End of Pass-through Enable (SMIATENDPS) — R/W. May need to cause SMI at the end of
a pass-through. Can occur if an SMI is generated in the middle of a pass through, and needs to be
serviced later.
0 = Disable
1 = Enable
NOTE:Setting this bit in any controller enables the function.
Pass Through State (PSTATE) — RO.
0 = If software needs to reset this bit, it should set bit 5 in all of the host controllers to 0.
1 = Indicates that the state machine is in the middle of an A20GATE pass-through sequence.
NOTE:This bit reports same value in all USB UHCI controllers.
A20Gate Pass-Through Enable (A20PASSEN) — R/W.
0 = Disable.
1 = Allows A20GATE sequence Pass-Through function. A specific cycle sequence involving writes to
NOTE:Setting this bit in any controller enables the function.
SMI on USB IRQ Enable (USBSMIEN) — R/W.
0 = Disable
1 = USB interrupt will cause an SMI event.
SMI on Port 64 Writes Enable (64WEN) — R/W.
0 = Disable
1 = A 1 in bit 11 will cause an SMI event.
NOTE:Setting this bit in any controller enables the function.
SMI on Port 64 Reads Enable (64REN) — R/W.
0 = Disable
1 = A 1 in bit 10 will cause an SMI event.
NOTE:Setting this bit in any controller enables the function.
SMI on Port 60 Writes Enable (60WEN) — R/W.
0 = Disable
1 = A 1 in bit 9 will cause an SMI event.
NOTE:Setting this bit in any controller enables the function.
SMI on Port 60 Reads Enable (60REN) — R/W.
0 = Disable
1 = A 1 in bit 8 will cause an SMI event.
NOTE:Setting this bit in any controller enables the function.
Reserved
port 60h and 64h does not result in the setting of the SMI status bits.
C4h
00h
Description
Description
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W
8 bits