FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 187

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.16.1.2
Intel
®
Figure 5-16. Transfer Descriptor
Table 5-57. TD Link Pointer
82801DBM ICH4-M Datasheet
Transfer Descriptor (TD)
Transfer Descriptors (TDs) express the characteristics of the transaction requested on USB by a
client. TDs are always aligned on 16-byte boundaries, and the elements of the TD are shown in
Figure
in the descriptor that the ICH4 interprets during operation. All Transfer Descriptors have the same
basic, 32-byte structure. During operation, the ICH4 hardware performs consistency checks on
some fields of the TD. If a consistency check fails, the ICH4 halts immediately and issues an
interrupt to the system. This interrupt cannot be masked within the ICH4.
R = Reserved
31:4
31
Bit
3
2
1
0
R
ICH4 Read/Write
30
5-16. The four different USB transfer types are supported by a small number of control bits
SPD
29
Link Pointer (LP). Bits [31:4] Correspond to memory address signals [31:4], respectively. This field
points to another TD or QH.
Reserved. Must be 0 when writing this field.
Depth/Breadth Select (VF). This bit is only valid for queued TDs and indicates to the hardware
whether it should process in a depth first or breadth first fashion. When set to depth first, it informs
the ICH4 to process the next transaction in the queue rather than starting a new queue.
0 = Breadth first
1 = Depth first
QH/TD Select (Q). This bit informs the ICH4 whether the item referenced by the link pointer is
another TD or a QH. This allows the ICH4 to perform the proper type of processing on the item after
it is fetched.
0 = TD
1 = QH
Terminate (T). This bit informs the ICH4 that the link pointer in this TD does not point to another
valid entry. When encountered in a queue context, this bit indicates to the ICH4 that there are no
more valid entries in the queue. A TD encountered outside of a queue context with the T bit set
informs the ICH4 that this is the last TD in the frame.
0 = Link Pointer field is valid.
1 = Link Pointer field not valid.
28
C_ERR LS
MaxLen
27
26
ISO ISC
25
24
23
ICH4 Read Only
21
Link Pointer
20
Status
R
19
D
Buffer Pointer
18
EndPt
Description
16
15
14
R
Device Address
11
10
8
Functional Description
7
ActLen
PID
4
3
0
Vf
2
1
Q
0
T
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