FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 182

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.15.2.6
5.15.2.7
5.15.3
182
Table 5-54. Interrupt/Active Bit Interaction Definition
Error Conditions
IDE devices are sector-based mass storage devices. The drivers handle errors on a sector basis;
either a sector is transferred successfully or it is not. A sector is 512 bytes.
If the IDE device does not complete the transfer due to a hardware or software error, the command
will eventually be stopped by the driver setting Command Start bit to 0 when the driver times out
the disk transaction. Information in the IDE device registers help isolate the cause of the problem.
If the controller encounters an error while doing the bus master transfers it will stop the transfer
(i.e., reset the Active bit in the Command register) and set the Error bit in the Bus Master IDE
Status register. The controller does not generate an interrupt when this happens. The device driver
can use device specific information (PCI Configuration Space Status register and IDE Drive
Register) to determine what caused the error.
When a requested transfer does not complete properly, information in the IDE device registers
(Sector Count) can be used to determine how much of the transfer was completed and to construct
a new PRD table to complete the requested operation. In most cases the existing PRD table can be
used to complete the operation.
8237-Like Protocol
The 8237 mode DMA is similar in form to DMA used on the ISA bus. This mode uses pins
familiar to the ISA bus, namely a DMA Request, a DMA Acknowledge, and I/O read/write strobes.
These pins have similar characteristics to their ISA counterparts in terms of when data is valid
relative to strobe edges, and the polarity of the strobes; however, the ICH4 does not use the 8237
for this mode.
Ultra ATA/33 Protocol
Ultra ATA/33 is enabled through configuration register 48h in Device 31:Function 1 for each IDE
device. The IDE signal protocols are significantly different under this mode than for 8237 mode.
Ultra ATA/33 is a physical protocol used to transfer data between a Ultra ATA/33 capable IDE
controller (e.g., the ICH4) and one or more Ultra ATA/33 capable IDE devices. It utilizes the
standard Bus Master IDE functionality and interface to initiate and control the transfer.
Ultra ATA/33 utilizes a “source synchronous” signaling protocol to transfer data at rates up to
33 MB/s. The Ultra ATA/33 definition also incorporates a Cyclic Redundancy Checking (CRC-16)
error checking protocol.
Interrupt
0
1
1
0
Active
1
0
1
0
DMA transfer is in progress. No interrupt has been generated by the IDE device.
The IDE device generated an interrupt. The controller exhausted the Physical Region
Descriptors. This is the normal completion case where the size of the physical memory
regions was equal to the IDE device transfer size.
The IDE device generated an interrupt. The controller has not reached the end of the
physical memory regions. This is a valid completion case where the size of the physical
memory regions was larger than the IDE device transfer size.
This bit combination signals an error condition. If the Error bit in the status register is set,
then the controller has some problem transferring data to/from memory. Specifics of the
error have to be determined using bus-specific information. If the Error bit is not set, then
the PRD's specified a smaller size than the IDE transfer size.
Description
Intel
®
82801DBM ICH4-M Datasheet