FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 459

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

12.2.2.2
Intel
®
82801DBM ICH4-M Datasheet
EHCI_STS—USB EHCI Status Register
Offset:
Default Value:
This register indicates pending interrupts and various states of the Host Controller. The status
resulting from a transaction on the serial bus is not indicated in this register. Software sets a bit to 0
in this register by writing a 1 to it. See the Interrupts description in Chapter 4 of the Enhanced Host
Controller Interface (EHCI) Specification for Universal Serial Bus for additional information
concerning USB EHCI interrupt conditions.
31:16
11:6
Bit
15
14
13
12
5
4
Reserved. Should be set to 0s.
Asynchronous Schedule Status  RO. This bit reports the current real status of the Asynchronous
Schedule. The Host Controller is not required to immediately disable or enable the Asynchronous
Schedule when software transitions the Asynchronous Schedule Enable bit in the USBCMD register.
When this bit and the Asynchronous Schedule Enable bit are the same value, the Asynchronous
Schedule is either enabled (1) or disabled (0).
0 = Disable. (Default)
1 = Enable. The status of the Asynchronous Schedule is enabled.
Periodic Schedule Status  RO. This bit reports the current real status of the Periodic Schedule.
The Host Controller is not required to immediately disable or enable the Periodic Schedule when
software transitions the Periodic Schedule Enable bit in the USBCMD register. When this bit and the
Periodic Schedule Enable bit are the same value, the Periodic Schedule is either enabled (1) or
disabled (0).
0 = Disable. (Default).
1 = Enable. The status of the Periodic Schedule is enabled.
Reclamation  RO. (Defaults to 1). This bit is used to detect an empty asynchronous schedule. The
operational model and valid transitions for this bit are described in Section 4 of the EHCI
Specification.
HCHalted  RO.
0 = This bit is a 0 when the Run/Stop bit is a 1.
1 = The Host Controller sets this bit to 1 after it has stopped executing as a result of the Run/Stop
Reserved
Interrupt on Async Advance — R/WC. 0=Default.
0 = Interrupt not occurred (source not asserted).
1 = Interrupt occurred (source asserted). System software can force the host controller to issue an
Host System Error — RO.
0 = No host system error during access of the Host Controller module.
1 = Host system error. The Host Controller sets this bit to 1 when a serious error occurs during a
bit being set to 0, either by software or by the Host Controller hardware (e.g., internal error).
(Default)
interrupt the next time the host controller advances the asynchronous schedule by writing a 1 to
the Interrupt on Async Advance Doorbell bit in the USBCMD register. This bit indicates the
assertion of that interrupt source.
host system access involving the Host Controller module. A hardware interrupt is generated to
the system. Memory read cycles initiated by the EHC that receive any status other than
Successful will result in this bit being set.
When this error occurs, the Host Controller clears the Run/Stop bit in the Command register to
prevent further execution of the scheduled TDs. A hardware interrupt is generated to the
system (if enabled in the Interrupt Enable Register).
CAPLENGTH + 04
00001000h
–
07h
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/WC, RO
32 bits
459