FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 52

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Signal Description
2.10
52
Table 2-10. Power Management Interface Signals (Sheet 1 of 2)
Power Management Interface
THRM#
THRMTRIP#
SLP_S1#
SLP_S3#
SLP_S4#
SLP_S5#
PWROK
PWRBTN#
RI#
SYS_RESET#
RSMRST#
LAN_RST#
SUS_STAT# /
LPCPD#
Name
Type
O
O
O
O
O
I
I
I
I
I
I
I
I
Thermal Alarm: This is an active low signal generated by external hardware to
start the hardware clock throttling mode. The signal can also generate an SMI#
or an SCI.
Thermal Trip: When low, THRMTRIP# indicates that a thermal trip from the
processor occurred; the ICH4 will immediately transition to a S5 state. The ICH4
will not wait for the processor stop grant cycle since the processor has
overheated.
S1 Sleep Control: SLP_S1# provides Clock Synthesizer or Power plane
control. Optional use is to shut off power to non-critical systems when in the S1-
M (Powered On Suspend), S3 (Suspend To RAM), S4 (Suspend to Disk) or S5
(Soft Off) states.
S3 Sleep Control: SLP_S3# is for power plane control. It shuts off power to all
non-critical systems when in S3 (Suspend To RAM), S4 (Suspend to Disk), or
S5 (Soft Off) states.
S4 Sleep Control: SLP_S4# is for power plane control. It shuts power to all
non-critical systems when in the S4 (Suspend to Disk) or S5 (Soft Off) state.
S5 Sleep Control: SLP_S5# is for power plane control. The signal is used to
shut power off to all non-critical systems when in the S5 (Soft Off) states.
Power OK: When asserted, PWROK is an indication to the ICH4 that core
power and PCICLK have been stable for at least 1 ms. PWROK can be driven
asynchronously. When PWROK is negated, the ICH4 asserts PCIRST#.
NOTE: PWROK must deassert for a minimum of 3 RTC clock periods for the
Power Button: The Power Button causes SMI# or SCI to indicate a system
request to go to a sleep state. If the system is already in a sleep state, this signal
causes a wake event. If PWRBTN# is pressed for more than 4 seconds, this
causes an unconditional transition (power button override) to the S5 state with
only the PWRBTN# available as a wake event. Override occurs even if the
system is in the S1-M–S4 states. This signal has an internal pull-up resistor.
Ring Indicate: This signal is an input from the modem interface. It can be
enabled as a wake event, and this is preserved across power failures.
System Reset: This pin forces an internal reset after being debounced. The
ICH4 will reset immediately if the SMBus is idle; otherwise, it will wait up to
25 ms ± 2 ms for the SMBus to idle before forcing a reset on the system.
Resume Well Reset: This signal is used for resetting the resume power plane
logic.
LAN Reset: This signal must be asserted at least 10 ms after the resume well
power (VccLAN3_3 and VccLAN1_5 is valid. When deasserted, this signal is an
indication that the resume well power is stable.
Suspend Status: This signal is asserted by the ICH4 to indicate that the system
will be entering a low power state soon. This can be monitored by devices with
memory that need to switch from normal refresh to suspend refresh mode. It can
also be used by other peripherals as an indication that they should isolate their
outputs that may be going to powered-off planes. This signal is called LPCPD#
on the LPC I/F.
ICH4 to fully reset the power and properly generate the PCIRST#
output
Description
Intel
®
82801DBM ICH4-M Datasheet