FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 461

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

12.2.2.3
Intel
®
82801DBM ICH4-M Datasheet
EHCI_INTR—USB EHCI Interrupt Enable Register
Offset:
Default Value:
This register enables and disables reporting of the corresponding interrupt to the software. When a
bit is set and the corresponding interrupt is active, an interrupt is generated to the host. Interrupt
sources that are disabled in this register still appear in the Status Register to allow the software to
poll for events. Each interrupt enable bit description indicates whether it is dependent on the
interrupt threshold mechanism, or not (see Chapter 4 of the Enhanced Host Controller Interface
(EHCI) Specification for Universal Serial Bus).
31:6
Bit
5
4
3
2
1
0
Reserved. Should be 0s.
Interrupt on Async Advance Enable — R/W. When this bit is a 1, and the Interrupt on Async
Advance bit in the EHCI_STS register is a 1, the host controller will issue an interrupt at the next
interrupt threshold. The interrupt is acknowledged by software clearing the Interrupt on Async
Advance bit in the EHCI_STS register.
0 = Disable
1 = Enable
Host System Error Enable — R/W. When this bit is a 1, and the Host System Error Status bit in the
EHCI_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged
by software clearing the Host System Error bit in the EHCI_STS register.
0 = Disable
1 = Enable
Frame List Rollover Enable — R/W. When this bit is a 1, and the Frame List Rollover bit in the
EHCI_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged
by software clearing the Frame List Rollover bit in the EHCI_STS register.
0 = Disable
1 = Enable
Port Change Interrupt Enable — R/W. When this bit is a 1, and the Port Change Detect bit in the
EHCI_STS register is a 1, the host controller will issue an interrupt. The interrupt is acknowledged
by software clearing the Port Change Detect bit in the EHCI_STS register.
0 = Disable
1 = Enable
USB Error Interrupt Enable — R/W. When this bit is a 1, and the USBERRINT bit in the EHCI_STS
register is a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt
is acknowledged by software by clearing the USBERRINT bit in the EHCI_STS register.
0 = Disable
1 = Enable
USB Interrupt Enable — R/W. When this bit is a 1, and the USBINT bit in the EHCI_STS register is
a 1, the host controller will issue an interrupt at the next interrupt threshold. The interrupt is
acknowledged by software by clearing the USBINT bit in the EHCI_STS register.
0 = Disable
1 = Enable
CAPLENGTH + 08
00000000h
–
0Bh
Description
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/W
32 bits
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