FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 15

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Intel
®
82801DBM ICH4-M Datasheet
9.2
9.3
9.4
9.5
9.1.25 RTC_CONF—RTC Configuration Register (LPC I/F—D31:F0)......320
9.1.26 COM_DEC—LPC I/F Communication Port Decode Ranges
9.1.27 FDD/LPT_DEC—LPC I/F FDD & LPT Decode Ranges
9.1.28 SND_DEC—LPC I/F Sound Decode Ranges
9.1.29 FWH_DEC_EN1—FWH Decode Enable 1 Register
9.1.30 GEN1_DEC—LPC I/F Generic Decode Range 1 Register
9.1.31 LPC_EN—LPC I/F Enables Register (LPC I/F—D31:F0)...............323
9.1.32 FWH_SEL1—FWH Select 1 Register (LPC I/F—D31:F0) ..............325
9.1.33 GEN2_DEC—LPC I/F Generic Decode Range 2 Register
9.1.34 FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0) ..............326
9.1.35 FWH_DEC_EN2—FWH Decode Enable 2 Register
9.1.36 FUNC_DIS—Function Disable Register (LPC I/F—D31:F0) ..........328
DMA I/O Registers .......................................................................................330
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
9.2.8
9.2.9
9.2.10 DMA_CLMSK—DMA Clear Mask Register ....................................335
9.2.11 DMA_WRMSK—DMA Write All Mask Register ..............................335
Timer I/O Registers......................................................................................336
9.3.1
9.3.2
9.3.3
8259 Interrupt Controller (PIC) Registers ....................................................339
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10 ELCR2—Slave Controller Edge/Level Triggered Register .............346
Advanced Interrupt Controller (APIC) ..........................................................347
9.5.1
9.5.2
(LPC I/F—D31:F0) ..........................................................................319
(LPC I/F—D31:F0) ..........................................................................320
(LPC I/F—D31:F0) ..........................................................................321
(LPC I/F—D31:F0) ..........................................................................321
(LPC I/F—D31:F0) ..........................................................................322
(LPC I/F—D31:F0) ..........................................................................323
(LPC I/F—D31:F0) ..........................................................................326
(LPC I/F—D31:F0) ..........................................................................327
DMABASE_CA—DMA Base and Current Address Registers ........331
DMABASE_CC—DMA Base and Current Count Registers............331
DMAMEM_LP—DMA Memory Low Page Registers ......................332
DMACMD—DMA Command Register ............................................332
DMASTA—DMA Status Register....................................................333
DMA_WRSMSK—DMA Write Single Mask Register ......................333
DMACH_MODE—DMA Channel Mode Register............................334
DMA Clear Byte Pointer Register ...................................................334
DMA Master Clear Register ............................................................335
TCW—Timer Control Word Register ..............................................336
9.3.1.1
9.3.1.2
SBYTE_FMT—Interval Timer Status Byte Format Register ...........338
Counter Access Ports Register.......................................................338
ICW1—Initialization Command Word 1 Register ............................340
ICW2—Initialization Command Word 2 Register ............................341
ICW3—Master Controller Initialization Command Word 3 Register341
ICW3—Slave Controller Initialization Command Word 3 Register .342
ICW4—Initialization Command Word 4 Register ............................342
OCW1—Operational Control Word 1 (Interrupt Mask) Register .....342
OCW2—Operational Control Word 2 Register ...............................343
OCW3—Operational Control Word 3 Register ...............................344
ELCR1—Master Controller Edge/Level Triggered Register ...........345
APIC Register Map .........................................................................347
IND—Index Register .......................................................................348
RDBK_CMD—Read Back Command..............................337
LTCH_CMD—Counter Latch Command .........................337
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