FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 149

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.12.6.3
5.12.6.4
5.12.6.5
Intel
®
82801DBM ICH4-M Datasheet
Conditions for Stopping the PCI Clock
Behavioral Description
Conditions for Re-Starting the PCI Clock
Behavioral Description
If an internal source requests the clock to be re-started, the ICH4 re-asserts CLKRUN#, and
simultaneously deasserts the STP_PCI# signal.
Other Causes of CLKRUN# Going Active
The following causes the ICH4 to assert and/or maintain the CLKRUN# signal active (low):
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If no device re-asserts CLKRUN# once it has been deasserted for 3 clocks, the ICH4 stops the
PCI clock by asserting the STP_PCI# signal to the clock synthesizer.
A peripheral asserts CLKRUN# to indicate that it needs the PCI clock re-started.
When the ICH4 observes the CLKRUN# signal asserted for 1 (free running) clock, the ICH4
deasserts the STP_PCI# signal to the clock synthesizer within 4 (free running) clocks.
Observing the CLKRUN# signal asserted externally for 1 (free running) clock, the ICH4 again
starts driving CLKRUN# asserted.
PC/PCI activity, which is started by one of the REQx# signals going active. It is expected that
a PC/PCI device will assert CLKRUN# prior to starting the start bit on the REQ# signal. Once
the start bit is recognized, the ICH4 makes sure CLKRUN# goes active if it should go inactive
during the sequence.
SERIRQ activity, which is started by the SERIRQ signal going low (in quiet mode), or the
SERIRQ logic being in the continuous mode. It is expected that a SERIRQ device will assert
CLKRUN# prior to starting the start bit on the SEIRQ signal. One the start bit is recognized,
the ICH4 makes sure CLKRUN# goes active if it should go inactive during the sequence.
Any internal or external bus master request, including LPC masters. Once the master request is
detected (via PCI REQ or LPC LDRQ[1:0]#), the ICH4 maintains CLKRUN# active until the
end of the sequence. This includes:
Any bus master below PCI that needs to run a cycle. This could include the Processor System
Bus interrupt logic for the I/O APIC, if it is downstream of PCI.
— Any PCI REQ# low
— Bus Master or DMA request pending (having come in via LDRQ[1:0]#)
— Any cycle coming down from hub interface1 to PCI
— Any PCI cycle currently in progress. For example, cycle forward by ICH4 from the hub
interface to PCI, and then claimed by ICH4's PCI-to-LPC logic. That cycle is run as a
Delayed Transaction on PCI. CLKRUN# should stay low until the cycle completes
(without Delayed Transaction).
Functional Description
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