FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 470

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

EHCI Controller Registers (D29:F7)
12.2.3.2
12.2.3.3
470
USB PIDs Register
Offset:
Default Value:
This DWord register is used to communicate PID information between the USB debug driver and
the USB debug port. The debug port uses some of these fields to generate USB packets, and uses
other fields to return PID information to the USB debug driver.
Data Buffer Bytes 7:0 Register
Offset:
Default Value:
This register can be accessed as 8 separate 8-bit registers or 2 separate 32-bit register.
31:24
23:16
15:8
63:0
7:0
Bit
Bit
Reserved. These bits will return 0 when read. Writes will have no effect.
RECEIVED_PID_STS [23:16] — RO. The hardware updates this field with the received PID for
transactions in either direction. When the controller is writing data, this field is updated with the
handshake PID that is received from the device. When the host controller is reading data, this field
is updated with the data packet PID (if the device sent data), or the handshake PID (if the device
NAKs the request). This field is valid when the hardware clears the GO_DONE#_CNT bit.
SEND_PID_CNT [15:8] — R/W. The hardware sends this PID to begin the data packet when
sending data to USB (i.e., WRITE_READ#_CNT is asserted). Software will typically set this field to
either DATA0 or DATA1 PID values.
TOKEN_PID_CNT [7:0] — R/W. Hardware sends this PID as the Token PID for each USB
transaction. Software typically sets this field to either IN, OUT, or SETUP PID values.
DATA_BUFFER [63:0] — R/W. These are the 8 bytes of the data buffer. The bytes in the Data
Buffer must be written with data before software initiates a write request. For a read request, the
Data Buffer contains valid data when DONE_STS bit is cleared by the hardware,
ERROR_GOOD#_STS is cleared by the hardware, and the DATA_LENGTH_CNT field indicates
the number of bytes that are valid.
Bits 63:56Correspond to the most significant byte (byte 7).
...
...
Bits 7:0Correspond to least significant byte (byte 0).
04h
00000000h
0000000000000000h
08h
Description
Description
Attribute:
Size:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W, RO
32 bits
R/W
64 bits