FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 106

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.5.9
5.5.10
106
Abandoning DMA Requests
DMA Requests can be deasserted in two fashions: on error conditions by sending an LDRQ#
message with the ‘ACT’ bit set to 0, or normally through a SYNC field during the DMA transfer.
This section describes boundary conditions where the DMA request needs to be removed prior to a
data transfer.
There may be some special cases where the peripheral desires to abandon a DMA transfer. The
most likely case of this occurring is due to a floppy disk controller which has overrun or underrun
its FIFO, or software stopping a device prematurely.
In these cases, the peripheral wishes to stop further DMA activity. It may do so by sending an
LDRQ# message with the ACT bit as 0. However, since the DMA request was seen by the ICH4,
there is no guarantee that the cycle has not been granted and will shortly run on LPC. Therefore,
peripherals must take into account that a DMA cycle may still occur. The peripheral can choose not
to respond to this cycle, in which case the host will abort it, or it can choose to complete the cycle
normally with any random data.
This method of DMA deassertion should be prevented whenever possible, to limit boundary
conditions both on the ICH4 and the peripheral.
General Flow of DMA Transfers
Arbitration for DMA channels is performed through the 8237 within the host. Once the host has
won arbitration on behalf of a DMA channel assigned to LPC, it asserts LFRAME# on the LPC
interface and begins the DMA transfer. The general flow for a basic DMA transfer is as follows:
1. ICH4 starts transfer by asserting 0000b on LAD[3:0] with LFRAME# asserted.
2. ICH4 asserts ‘cycle type’ of DMA, direction based on DMA transfer direction.
3. ICH4 asserts channel number and, if applicable, terminal count.
4. ICH4 indicates the size of the transfer: 8 or 16 bits.
5. If a DMA read…
6. If a DMA write…
7. The peripheral turns around the bus.
— The ICH4 drives the first 8 bits of data and turns the bus around.
— The peripheral acknowledges the data with a valid SYNC.
— If a 16 bit transfer, the process is repeated for the next 8 bits.
— The ICH4 turns the bus around and waits for data.
— The peripheral indicates data ready through SYNC and transfers the first byte.
— If a 16 bit transfer, the peripheral indicates data ready and transfers the next byte.
Intel
®
82801DBM ICH4-M Datasheet