FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 375

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.8.3.6
Intel
®
82801DBM ICH4-M Datasheet
LV2 — Level 2 Register
I/O Address:
Default Value:
Lockable:
Power Well:
3:1
7:0
Bit
Bit
4
0
THTL_EN — R/W. When set and the system is in a C0 state, it enables a processor-controlled
STPCLK# throttling. The duty cycle is selected in the THTL_DTY field.
0 = Disable
1 = Enable
THTL_DTY — R/W. This 3-bit field determines the duty cycle of the throttling when the THTL_EN bit
is set. The duty cycle indicates the approximate percentage of time the STPCLK# signal is asserted
(low) while in the throttle mode. The STPCLK# throttle period is 1024 PCICLKs.
THTL_DTY Throttle ModePCI Clocks
000 50% (Default)512
001 87.5%896
010 75.0%768
011 62.5%640
100 50%512
101 37.5%384
110 25%256
111 12.5%128
Reserved
Reads to this register return all zeros, writes to this register have no effect. Reads to this register
generate a “enter a level 2 power state” (C2) to the clock control logic. This will cause the STPCLK#
signal to go active, and stay active until a break event occurs. Throttling (due either to THTL_EN or
THRM# override) will be ignored.
PMBASE + 14h
(
00h
No
Core
ACPI P_BLK+4)
Description
Description
Attribute:
Size:
Usage:
LPC Interface Bridge Registers (D31:F0)
RO
8 bit
ACPI or Legacy
375