FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 306

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.1
9.1.2
306
Table 9-1. LPC I/F PCI Configuration Register Address Map (LPC I/F—D31:F0) (Sheet 2 of 2)
NOTE: Refer to the ICH4 Specification Update for the value of the Revision ID Register.
VID—Vendor ID Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
DID—Device ID Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
EC–EDh
EE–EFh
15:0
15:0
A0–CFh
D0–D3h
E8–EBh
E4–E5h
E6–E7h
Bit
Bit
Offset
D4h
D5h
D8h
E0h
E1h
E2h
E3h
F0h
F2h
Vendor Identification Value — RO . This is a 16-bit value assigned to Intel. Intel VID = 8086h
Device Identification Value — RO . This is a 16-bit value assigned to the ICH4 LPC Bridge.
FWH_DEC_EN1
FWH_DEC_EN2
LPCFDD_DEC
BACK_CNTL
GEN_CNTL
RTC_CONF
GEN1_DEC
GEN2_DEC
FWH_SEL1
FWH_SEL2
COM_DEC
FUNC_DIS
Mnemonic
SND_DEC
GEN_STA
LPC_EN
00
02
8086h
No
24CCh
No
–
–
01h
03h
Power Management Registers
(See
General Control
General Status
Backed Up Control
Real Time Clock Configuration
LPC I/F COM Port Decode Ranges
LPC I/F FDD & LPT Decode Ranges
LPC I/F Sound Decode Ranges
FWH Decode Enable 1
LPC I/F General 1 Decode Range
LPC I/F Enables
FWH Select 1
LPC I/F General 2 Decode Range
FWH Select 2
FWH Decode Enable 2
Function Disable Register
Section
Register Name
9.8.1)
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
Intel
®
82801DBM ICH4-M Datasheet
RO
16 bit
Core
RO
16 bit
Core
Depends on
00000000h
00112233h
Default
0000h
0000h
5678h
Strap
0Xh
FFh
0Fh
00h
00h
00h
00h
00h
00h
R/W-Special,
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
RO