FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 445

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

12.1.19
12.1.20
Intel
®
82801DBM ICH4-M Datasheet
PWR_CNTL_STS—Power Management Control/Status
Register (USB EHCI—D29:F7)
Address Offset:
Default Value:
NOTE: Reset (bits 15, 8): suspend well, and not D3-to-D0 warm reset nor core well reset.
DEBUG_CAPID—Debug Port Capability ID Register
(USB EHCI—D29:F7)
Address Offset:
Default Value:
14:13
12:9
7:2
1:0
7:0
Bit
Bit
15
8
PME Status — R/WC.
0 = Writing a 1 to this bit clears it and causes the internal PME to deassert (if enabled). Writing a 0
1 = This bit is set when the ICH4 EHC would normally assert the PME# signal independent of the
NOTE: This bit must be explicitly cleared by the operating system each time the operating system
Data Scale — RO. Hardwired to 00b; ICH4 does not support the associated Data register.
Data Select — RO. Hardwired to 0000b; ICH4 does not support the associated Data register.
PME Enable — R/W.
0 = Disable.
1 = Enables the ICH4 EHC to generate an internal PME signal when PME_Status is 1.
NOTE: This bit must be explicitly cleared by the operating system each time it is initially loaded.
Reserved
Power State — R/W. This 2-bit field is used both to determine the current power state of EHC
function and to set a new power state. The definition of the field values are:
00 = D0 state
11 = D3 hot state
If software attempts to write a value of 10b or 01b in to this field, the write operation must complete
normally; however, the data is discarded and no state change occurs. When in the D3 hot state, the
ICH4 must not accept accesses to the EHC memory range; but the configuration space must still be
accessible. When not in the D0 state, the generation of the interrupt output is blocked. Specifically,
the PIRQ[H] is not asserted by the ICH4 when not in the D0 state.
When software changes this value from the D3 hot state to the D0 state, an internal warm (soft)
reset is generated, and software must re-initialize the function.
Debug Port Capability ID — RO. Hardwired to 0Ah; indicates that this is the start of a Debug Port
Capability structure.
has no effect.
state of the PME_En bit.
is loaded.
54
0000h
58h
0Ah
–
55h
Description
Description
Attribute:
Size:
Attribute:
Size:
EHCI Controller Registers (D29:F7)
R/WC, R/W
16 bits
RO
8 bits
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