FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 326

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

LPC Interface Bridge Registers (D31:F0)
9.1.33
9.1.34
326
GEN2_DEC—LPC I/F Generic Decode Range 2 Register
(LPC I/F—D31:F0)
Offset Address:
Default Value:
Lockable:
FWH_SEL2—FWH Select 2 Register (LPC I/F—D31:F0)
Offset Address:
Default Value:
15:12
15:4
11:8
Bit
3:1
Bit
7:4
3:0
0
Generic I/O Decode Range 2 Base Address (GEN2_BASE) — R/W. This address is aligned on a
64-byte boundary, and must have address lines 31:16 as 0.
Note that this generic decode is for I/O addresses only, not memory addresses. The size of this
range is 16 bytes.
Reserved. Read as 0
Generic I/O Decode Range 2 Enable (GEN2_EN) — R/W.
0 = Disable.
1 = Accesses to the GEN2 I/O range will be forwarded to the LPC I/F
FWH_70_IDSEL — R/W. IDSEL for two 1M FWH memory ranges. The IDSEL programmed in this
field addresses the following memory ranges:
FF70 0000h
FF30 0000h
FWH_60_IDSEL — R/W. IDSEL for two 1M FWH memory ranges. The IDSEL programmed in this
field addresses the following memory ranges:
FF60 0000h
FF20 0000h
FWH_50_IDSEL — R/W. IDSEL for two 1M FWH memory ranges. The IDSEL programmed in this
field addresses the following memory ranges:
FF50 0000h
FF10 0000h
FWH_40_IDSEL — R/W. IDSEL for two 1M FWH memory ranges. The IDSEL programmed in this
field addresses the following memory ranges:
FF40 0000h
FF00 0000h
Yes
4567h
ECh–EDh
00h
EEh
–
–
–
–
–
–
–
–
FF7F FFFFh
FF3F FFFFh
FF6F FFFFh
FF2F FFFFh
FF5F FFFFh
FF1F FFFFh
FF4F FFFFh
FF0F FFFFh
–
EFh
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Intel
®
82801DBM ICH4-M Datasheet
R/W
16 bit
Core
R/W
32 bits