FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 244

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.19.1
244
Figure 5-21. Intel
Note: Throughout this document, references to D31:F5 indicate that the audio function exists in PCI
Note: Throughout this document, references to tertiary, third, or triple codecs refer to the third codec in
Device 31, Function 5. References to D31:F6 indicate that the modem function exists in PCI
Device 31, Function 6.
the system connected to the AC_SDIN[2] pin. The AC ’97 2.3 specification refers to non-primary
codecs as multiple secondary codecs. To avoid confusion and excess verbiage this datasheet refers
to it as the third or tertiary codec.
PCI Power Management
This Power Management section applies for all AC ’97 controller functions. After a power
management event is detected, the AC ’97 controller will wake the host system. The sections
below describe these events and the AC ’97 controller power states.
Device Power States
The AC ’97 controller supports D0 and D3 PCI Power Management states. Notes regarding the
Intel ICH4 AC ’97 controller implementation of the Device States:
10. Once the interrupt status bits are set, they will cause PIRQB# if their respective enable bits
1. The AC ’97 controller hardware does not inherently consume any more power when it is in the
2. In the D0 state, all implemented AC ’97 controller features are enabled.
3. In D3 state, accesses to the AC ’97 controller memory-mapped or I/O range result in master
4. In D3 state, the AC ’97 controller interrupt must never assert for any reason. The internal
5. When the Device Power State field is written from D3
6. AC ’97 STS bit will be set only when the audio or modem resume events were detected and
7. GPIO Status change interrupt no longer has a direct path to AC ’97 STS bit. This will cause a
8. Resume events on AC_SDIN[2:0] will cause resume interrupt status bits to be set only if their
9. Edge detect logic will prevent the interrupts from being asserted in case AC ’97 controller is
D0 state than it does in D3 state. However, software can halt the DMA engine prior to entering
these low power states such that the maximum power consumption is reduced.
abort.
PME# signal is used to signal wake events, etc.
See
their respective PME enable bits were set.
wake up event only if the modem controller was in D3
respective controllers are not in D3.
switched from D3 to D0 after a wake event.
were set. One of the audio or the modem drivers will handle the interrupt.
®
Section 14.1
ICH4 Based Audio Codec ’97 Specification, Revision 2.3
for general rules on the effects of this reset.
PC
Mic.2
HOT
Intel
to D0, an internal reset is generated.
Modem
Audio In (Record)
Audio Out (6 Channel Playback)
Mic.1
S/PDIF* Output
®
82801DBM ICH4-M Datasheet