FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 153

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.12.7.4
Intel
®
Table 5-42. Transitions Due to Power Failure
82801DBM ICH4-M Datasheet
Note: Although PME_EN is in the RTC well, this signal cannot wake the system after a power loss.
Sx-G3-Sx, Handling Power Failures
A power failure in a mobile system is a rare event, since the power subsystem should provide
sufficient warning when the batteries are low. However, if the user removes the battery or leaves
the system in an STR state for too long, a power failure could occur.
In either case, PWROK and RSMRST# are assumed to go low.
Depending on when the power failure occurs and how the system is designed, different transitions
could occur due to a power failure.
The AFTER_G3 bit provides the ability to program whether or not the system should boot once
power returns after a power loss event. If the policy is to not boot, the system will remain in an S5
state (unless previously in S4). There are only three possible events that will wake the system after
a power failure.
The ICH4 monitors both PWROK and RSMRST# to detect for power failures. If PWROK goes
low, the PWROK_FLR bit is set. If RSMRST# goes low, PWR_FLR is set.
PME_EN is cleared by RTCRST# and PME_STS is cleared by RSMRST#.
1. PWRBTN#: PWRBTN# is always enabled as a wake event. When RSMRST# is low
2. RI#: RI# does not have an internal pull-up. Therefore, if this signal is enabled as a wake event,
3. RTC Alarm: The RTC_EN bit is in the RTC well and is preserved after a power loss. Like
State at Power Failure
(G3 state), the PWRBTN_STS bit is reset. When the ICH4 exits G3 after power returns
(RSMRST# goes high), the PWRBTN# signal is already high (because VCC-standby goes
high before RSMRST# goes high) and the PWRBTN_STS bit is 0.
it is important to keep this signal powered during the power loss event. If this signal goes low
(active), when power returns, the RI_STS bit will be set and the system will interpret that as a
wake event.
PWRBTN_STS, the RTC_STS bit is cleared when RSMRST# goes low.
S0, S1-M, S3
S4
S5
AFTERG3_EN bit
1
0
1
0
1
0
Transition When Power Returns
Functional Description
S5
S0
S4
S0
S5
S0
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