FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 147

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

5.12.5.1
5.12.5.2
Intel
®
82801DBM ICH4-M Datasheet
Throttling Using STPCLK#
Throttling is used to lower power consumption or reduce heat. The ICH4 asserts STPCLK# to
throttle the processor clock and the processor appears to temporarily enter a C2 state. After a
programmable time, the ICH4 deasserts STPCLK# and the processor appears to return to the C0
state. This allows the processor to operate at reduced average power, with a corresponding decrease
in performance. Two methods are included to start throttling:
Throttling due to the THRM# signal has higher priority than the software-initiated throttling.
Throttling does not occur when the system is in a C2, C3, or C4, even if Thermal override occurs.
Transition Rules among S0/Cx and Throttling States
The following priority rules and assumptions apply among the various S0/Cx and throttling states:
1. Software enables a timer with a programmable duty cycle. The duty cycle is set by the
2. A Thermal Override condition (THRM# signal active for >2 seconds) occurs that
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THTL_DTY field and the throttling is enabled using the THTL_EN field. This is known as
Manual Throttling. The period is fixed to be in the non-audible range, due to the nature of
switching power supplies.
unconditionally forces throttling, independent of the THTL_EN bit. The throttling due to
Thermal Override has a separate duty cycle (THRM_DTY) which may vary by field and
system. The Thermal Override condition will end when THRM# goes inactive.
Entry to any S0/Cx state is mutually exclusive with entry to any S1-M–S5 state. This is
because the processor can only perform one register access at a time and Sleep states have
higher priority than thermal throttling.
When the SLP_EN bit is set (system going to a sleep state (S1-M–S5), the THTL_EN bit can
be internally treated as being disabled (no throttling while going to sleep state). Note that
thermal throttling (based on THRM# signal) cannot be disabled in an S0 state. However, once
the SLP_EN bit is set, the thermal throttling is shut off (since STPCLK# will be active in
S1-M–S5 states).
If the THTL_EN bit is set, and a Level 2, Level 3, or Level 4 read then occurs, the system
should immediately go and stay in aC2, C3, or C4 state until a break event occurs. A Level 2,
Level 3 or Level 4 read has higher priority than the software initiated throttling or thermal
throttling.
If Thermal Override is causing throttling, and a Level 2, Level 3, or Level 4 read then occurs,
the system will stay in a C2, C3, or C4 state until a break event occurs. A Level 2, Level 3 or
Level 4 read has higher priority than the Thermal Override.
After an exit from a C2, C3, or C4 state (due to a Break event), and if the THTL_EN bit is still
set, or if a Thermal Override is still occurring, the system will continue to throttle STPCLK#.
Depending on the time of break event, the first transition on STPCLK# active can be delayed
by up to one THRM period (1024 PCI clocks=30.72 microseconds).
The Host controller must post Stop-Grant cycles in such a way that the processor gets an
indication of the end of the special cycle prior to the ICH4 observing the Stop-Grant cycle.
This ensures that the STPCLK# signals stays active for a sufficient period after the processor
observes the response phase.
If in the C1 state and the STPCLK# signal goes active, the processor will generate a Stop-
Grant cycle, and the system should go to the C2 state. When STPCLK# goes inactive, it should
return to the C1 state.
Functional Description
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