FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 293
FW82801DBM S L6DN
Manufacturer Part Number
FW82801DBM S L6DN
Description
Manufacturer
Intel
Datasheet
1.FW82801DBM_S_L6DN.pdf
(615 pages)
Specifications of FW82801DBM S L6DN
Lead Free Status / RoHS Status
Not Compliant
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8.1.5
8.1.6
8.1.7
8.1.8
Intel
®
82801DBM ICH4-M Datasheet
RID—Revision Identification Register (HUB-PCI—D30:F0)
Offset:
Default Value:
SCC—Sub-Class Code Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
BCC—Base-Class Code Register (HUB-PCI—D30:F0)
Offset Address:
Default Value:
PMLT—Primary Master Latency Timer Register
(HUB-PCI—D30:F0)
Offset Address:
Default Value:
This register does not apply to hub interface.
7:0
7:0
7:3
2:0
Bit
Bit
Bit
Bit
7:0
Sub Class Code — RO. 8-bit value that indicates the category of bridge for the ICH4 hub interface to
PCI bridge. The code is 04h indicating a PCI-to-PCI bridge.
Base Class Code — RO. 8-bit value that indicates the type of device for the ICH4 hub interface to
PCI bridge. The code is 06h indicating a bridge device.
Master Latency Timer Count (MLTC). Not implemented.
Reserved
Revision Identification Value — RO. Refer to the ICH4 Specification Update for the value of the
Revision ID Register.e
08h
See Bit Description
0Ah
04h
0Bh
06h
0Dh
00h
Hub Interface to PCI Bridge Registers (D30:F0)
Description
Description
Description
Description
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
Size:
Attribute:
RO
8 Bits
RO
8 bits
RO
8 bits
RO
8 bits
293
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