FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 333

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

9.2.5
9.2.6
Intel
®
82801DBM ICH4-M Datasheet
DMASTA—DMA Status Register
I/O Address:
Default Value:
Lockable:
DMA_WRSMSK—DMA Write Single Mask Register
I/O Address:
Default Value:
Lockable:
7:4
3:0
7:3
1:0
Bit
Bit
2
Channel Request Status — RO. When a valid DMA request is pending for a channel, the
corresponding bit is set to 1. When a DMA request is not pending for a particular channel, the
corresponding bit is set to 0. The source of the DREQ may be hardware or a software request. Note
that channel 4 is the cascade channel, so the request status of channel 4 is a logical OR of the
request status for channels 0 through 3.
4 = Channel 0
5 = Channel 1 (5)
6 = Channel 2 (6)
7 = Channel 3 (7)
Channel Terminal Count Status — RO. When a channel reaches terminal count (TC), its status bit
is set to 1. If TC has not been reached, the status bit is set to 0. Channel 4 is programmed for
cascade, so the TC bit response for channel 4 is irrelevant:
0 = Channel 0
1 = Channel 1 (5)
2 = Channel 2 (6)
3 = Channel 3 (7)
Reserved. Must be 0.
Channel Mask Select — WO.
0 = Enable DREQ for the selected channel. The channel is selected through bits [1:0]. Therefore,
1 = Disable DREQ for the selected channel.
DMA Channel Select — WO. These bits select the DMA Channel Mode Register to program.
00 = Channel 0 (4)
01 = Channel 1 (5)
10 = Channel 2 (6)
11 = Channel 3 (7)
only one channel can be masked / unmasked at a time.
Ch. #0
Ch. #4
Undefined
No
Ch. #0
Ch. #4
0000 01xx
No
–
–
–
–
3 = 08h;
7 = D0h
3 = 0Ah;
7 = D4h
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
LPC Interface Bridge Registers (D31:F0)
RO
8 bit
Core
WO
8 bit
Core
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