FW82801DBM S L6DN Intel, FW82801DBM S L6DN Datasheet - Page 5

• Manufacturer Part Number: FW82801DBM S L6DN
• Manufacturer: Intel

Specifications of FW82801DBM S L6DN

• Lead Free Status / RoHS Status: Not Compliant

Contents
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2
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Intel
®
82801DBM ICH4-M Datasheet
Introduction
1.1
1.2
Signal Description
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
2.10
2.11
2.12
2.13
2.14
2.15
2.16
2.17
2.18
2.19
2.20
Intel
3.1
3.2
3.3
3.4
3.5
Intel
Functional Description
5.1
®
®
ICH4-M System Clock Domains
ICH4-M Power Planes and Pin States
About This Datasheet .................................................................................... 33
Overview ........................................................................................................ 36
Hub Interface to Host Controller .................................................................... 45
Link to LAN Connect ...................................................................................... 45
EEPROM Interface ........................................................................................ 46
Firmware Hub Interface ................................................................................. 46
PCI Interface .................................................................................................. 46
IDE Interface .................................................................................................. 49
LPC Interface ................................................................................................. 50
Interrupt Interface........................................................................................... 50
USB Interface................................................................................................. 51
Power Management Interface........................................................................ 52
Processor Interface........................................................................................ 54
SMBus Interface ............................................................................................ 55
System Management Interface ...................................................................... 55
Real Time Clock Interface.............................................................................. 56
Other Clocks .................................................................................................. 56
Miscellaneous Signals ................................................................................... 56
AC’97 Link...................................................................................................... 57
General Purpose I/O ...................................................................................... 58
Power and Ground......................................................................................... 59
Pin Straps ...................................................................................................... 60
2.20.1 Functional Straps .............................................................................. 60
2.20.2 External RTC Circuitry ...................................................................... 61
2.20.3 V5REF / Vcc3_3 Sequencing Requirements ....................................61
2.20.4 Test Signals ...................................................................................... 62
Power Planes................................................................................................. 63
Integrated Pull-Ups and Pull-Downs .............................................................. 64
IDE Integrated Series Termination Resistors................................................. 64
Output and I/O Signals Planes and States ....................................................65
Power Planes for Input Signals...................................................................... 69
Hub Interface to PCI Bridge (D30:F0)............................................................ 73
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
...........................................................................................................33
2.20.4.1 Test Mode Selection.......................................................... 62
PCI Bus Interface.............................................................................. 73
PCI-to-PCI Bridge Model .................................................................. 74
IDSEL to Device Number Mapping ................................................... 74
SERR# Functionality......................................................................... 74
Parity Error Detection........................................................................ 76
Standard PCI Bus Configuration Mechanism ................................... 77
..............................................................................................43
.....................................................................................73
........................................................71
............................................63
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